H10P50/287

Methods for fabricating semiconductor structures having transistor arrays with different pitches

The present disclosure describes a method for fabricating semiconductor structures having transistor arrays with different pitches. The method can include forming a first and second arrays of structures on a semiconductor substrate. The second array of structures can be blocked with a first mask while exposing the first array. A first treatment can be applied to the first array of structures. The first array of structures can be blocked with a second mask while exposing the second array of structures. A second treatment can be applied to the second array of structures, where the second treatment is different from the first treatment.

PLASMA PROCESSING METHOD AND PLASMA PROCESSING
20260052955 · 2026-02-19 · ·

A substrate processing method includes (a) providing a substrate including an underlying film and a metal-containing resist film in which a pattern is formed on the underlying film; (b) forming a metal-containing film on a surface of the metal-containing resist film; and (c) removing a residue of the metal-containing film together with at least a part of the metal-containing film.

Microwave providing apparatus, system including the same, and method of manufacturing semiconductor device

Provided is a system including a microwave source configured to generate microwaves, a branch apparatus including an input port connected to the microwave source, first and second chambers configured to process a wafer by using the microwaves, a first filter configured to transfer the microwaves to or cut off the microwaves from the first chamber, and connected to a first output port of the branch apparatus, and a second filter configured to transfer the microwaves to or cut off the microwaves from the second chamber, and connected to a second output port of the branch apparatus.

Method for cleaning semiconductor substrate, method for producing processed semiconductor substrate, and stripping composition

A semiconductor substrate cleaning method including removing an adhesive layer provided on a semiconductor substrate by use of a remover composition, wherein the remover composition contains a solvent but no salt; and the solvent includes an organic solvent represented by any of formulae (L0) to (L4). ##STR00001##

System and method to reduce layout dimensions using non-perpendicular process scheme

A semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and determines, for each layout, whether a non-perpendicular particle bombardment process should be utilized in conjunction with a photolithography process for forming the features of the layout in a wafer.

PROCESSING STACKED SUBSTRATES
20260068566 · 2026-03-05 ·

Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE USING MULTI-LAYER HARD MASK
20260068613 · 2026-03-05 ·

The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

Upper film-forming composition and method for producing phase-separated pattern

An upper layer film-forming composition exhibits good solubility in hydrophobic solvents and can bring about vertical alignment of a block copolymer without dissolution, swelling or the like of a layer containing the block copolymer formed on a substrate. This upper layer film-forming composition is used for phase separation of a layer containing a block copolymer formed on a substrate, and contains: (A) a copolymer containing a unit structure derived from a maleimide structure (a) and a unit structure derived from a styrene structure; and (B) as a solvent, a non-aromatic hydrocarbon compound that is a liquid at normal temperature and pressure.

Manufacturing method of patterning substrate, patterned substrate, and intermediate patterned substrate

An excellent method of manufacturing a patterned substrate which is capable of easily patterning an insulation layer to provide a patterned substrate even when a difficult-to-etch material is used for the insulation layer, a patterned substrate obtained thereby, and a patterned substrate intermediate thereof are provided. The method of manufacturing a patterned substrate with the insulation layer and an electrode layer stacked in this order on a substrate comprising: forming an organic resist material layer; irradiating the organic resist material layer with radiation or an electromagnetic wave of a wavelength of 10 to 780 nm and developing the organic resist material layer to form a first patterning layer; and removing the first patterning layer.

SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A conventional substrate processing apparatus for generating plasma cannot generate plasma with high density and thus throughput of substrate processing is low. In order to solve this problem, provided is a substrate processing apparatus including a reaction vessel; a gas introduction port installed at an upper end of the reaction vessel; an electrode installed along an outer circumference of the reaction vessel; a baffle installed between the upper end of the reaction vessel and an upper end of the electrode with a gap between an outer circumference of the baffle and an inner circumference of the reaction vessel along the outer circumference of the baffle; a fixing part attached to an inner plane of the baffle and disposed inside the outer circumference of the baffle so as to fix the baffle to the upper end of the reaction vessel; and a gas exhaust pipe connected to the reaction vessel.