A semiconductor device includes a substrate, a plurality of metal lines on the substrate, a protuberance layer formed on upper portions of sidewalls of the metal lines, anda liner layer formed between the metal lines and between the protuberance layer. The liner layer connects the protuberance layer, and an airgap exists in the liner layer below a bottom surface of the protuberance layers.

The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

An integrated chip includes a first metal line disposed over a substrate. A via is disposed directly over a top of the first metal line and the via has a first lower surface and a second lower surface above the first lower surface. A first dielectric structure is disposed laterally adjacent to the first metal line and along a sidewall of the first metal line. A first protective etch-stop structure is disposed directly over a top of the first dielectric structure and vertically separates the second lower surface of the via from the top of the first dielectric structure.

Structures for an electronic fuse and methods of forming an electronic fuse. The structure comprises an electronic fuse including a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The first terminal, the second terminal, and the fuse link each include a semiconductor layer and a silicide layer. The silicide layer includes a first portion on the first terminal, a second portion on the second terminal, and a third portion on the fuse link. The fuse link includes an airgap between the semiconductor layer and the third portion of the silicide layer.

A semiconductor structure having metallization airgaps for subtractive metal processes and a method for making the same are disclosed. In an aspect, the semiconductor structure includes metal traces disposed above an adhesion layer and separated from each other in a horizontal direction by one or more airgaps having a height H. A dielectric layer is disposed above the metal traces but not above the airgaps. An etch stop layer (ESL) is disposed above the first dielectric layer and the airgaps. Each airgap extends from the top surface of the adhesion layer to the bottom surface of the first ESL and has a width that extends in the second horizontal direction from a side surface of the first metal trace, from a side surface of the second metal trace, or from the first metal trace to the second metal trace, depending on the pitch of the metal traces.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

A method of manufacturing a sacrificial layer may include providing a first compound including an amine compound including at least one secondary amine and a second compound including an isocyanate compound, and forming a sacrificial layer including polyurea through a polymerization reaction of the first compound and the second compound.

A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.