A semiconductor structure manufacturing method includes forming a base having a substrate and a dielectric layer on the substrate; forming a first metal layer on the base, the first metal layer has a plurality of first metal lines spaced apart from each other and partially covers the base; forming a dielectric landing layer to cover top surfaces and sidewalls of the plurality of first metal lines; forming a hollow dielectric layer on the dielectric landing layer between adjacent first metal lines; forming an interlayer dielectric layer to cover top surfaces of the hollow dielectric layer and the dielectric landing layer; etching the interlayer dielectric layer and the dielectric landing layer to form a plurality of trenches that expose the plurality of first metal lines; and depositing a metal material in the plurality of trenches to form a second metal layer.

A semiconductor device includes a substrate, a conductive interconnect structure disposed on the substrate, a plurality of air gap structures disposed on the conductive interconnect structure and spaced apart from each other, and a plurality of conductive interconnects disposed on the conductive interconnect structure and alternating with the plurality of the air gap structures. Each of the plurality of the air gap structures includes a dielectric portion and an air gap. The air gap of each of the plurality of the air gap structures is confined by the dielectric portion of the each of the plurality of the air gap structures and two corresponding ones of the plurality of the conductive interconnects.

A semiconductor device includes a gate structure on a substrate, a contact etch stop layer (CESL) on the gate structure, an interlayer dielectric (ILD) layer on the CESL, a first contact plug in the ILD layer and adjacent to the gate structure, a first stop layer on the ILD layer, an inter-metal dielectric (IMD) layer on the first stop layer, a first metal interconnection in the IMD layer, and an air gap around the gate structure and exposing the CESL and the first metal interconnection.

A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: forming a sacrificial layer in a concave in a metal layer; recessing the sacrificial layer; filling a metal-organic framework layer in the concave; and removing the sacrificial layer to form an air gap in the concave.

According to some example embodiments, an integrated circuit includes a first inter-wiring insulating film on a substrate, a first and second wiring patterns spaced apart from each other on the first inter-wiring insulating film, a first etch stop layer on the first inter-wiring insulating film, the first and second wiring patterns, and a second inter-wiring insulating film on the first etch stop layer. Each of the first and second wiring patterns includes a first lower pattern in the first inter-wiring insulating film, and a first upper pattern on an upper surface of the first inter-wiring insulating film. The first etch stop layer extends along profiles of the upper surface of the first inter-wiring insulating film, and a side face and an upper surface of the first upper pattern. The second inter-wiring insulating film defines a first void between the first wiring pattern and the second wiring pattern.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

Techniques are provided herein for forming backend memory structures with airgaps in an interconnect region above semiconductor devices. The airgaps may be provided between conductive features, such as wordlines, to reduce parasitic capacitance. An interconnect region above a plurality of semiconductor devices includes any number of interconnect layers. A first interconnect layer includes first conductive layers (e.g., wordlines) extending in a first direction with airgaps between adjacent first conductive layers. A second interconnect layer over the first interconnect layer includes at least portions of memory cells over corresponding first conductive layers. A third interconnect layer over the second interconnect layer includes a second conductive layer (e.g., bitline) extending in a second direction over one or more of the at least portions of memory cells. The presence of airgaps between the first conductive layers allows for a tighter pitch between memory cells and reduced total energy consumption among the memory cells.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first conductive layer formed over a substrate, and an air gap structure adjacent to the first conductive layer. The semiconductor device structure includes a support layer formed over the air gap structure, and a sidewall surface of the support layer is aligned with a sidewall surface of the air gap structure.