A semiconductor structure manufacturing method includes forming a base having a substrate and a dielectric layer on the substrate; forming a first metal layer on the base, the first metal layer has a plurality of first metal lines spaced apart from each other and partially covers the base; forming a dielectric landing layer to cover top surfaces and sidewalls of the plurality of first metal lines; forming a hollow dielectric layer on the dielectric landing layer between adjacent first metal lines; forming an interlayer dielectric layer to cover top surfaces of the hollow dielectric layer and the dielectric landing layer; etching the interlayer dielectric layer and the dielectric landing layer to form a plurality of trenches that expose the plurality of first metal lines; and depositing a metal material in the plurality of trenches to form a second metal layer.

Methods, systems, and devices for techniques for concurrently-formed cavities in three-dimensional memory arrays are described. As part of forming a memory die, a plurality of cavities may be formed by a set of one or more material removal operations, and different subsets of the plurality of cavities may be used to form different features of the memory die. In some examples, a sacrificial region may be formed in accordance with one or more material addition or removal operations, and such a sacrificial region may include openings that support the formation of various structures of a memory device. After the formation of such structures, the sacrificial region may be isolated from an active region by merging a subset of the previously-formed plurality of cavities.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

A semiconductor device includes a substrate, a conductive interconnect structure disposed on the substrate, a plurality of air gap structures disposed on the conductive interconnect structure and spaced apart from each other, and a plurality of conductive interconnects disposed on the conductive interconnect structure and alternating with the plurality of the air gap structures. Each of the plurality of the air gap structures includes a dielectric portion and an air gap. The air gap of each of the plurality of the air gap structures is confined by the dielectric portion of the each of the plurality of the air gap structures and two corresponding ones of the plurality of the conductive interconnects.

A structure includes boron nitride nanotubes, wherein the structure (i) is an extension region in a field-effect transistor or (ii) comprises a metallic interconnect to reduce the dielectric constant and therefore the RC-delay in the device. Also, a field-effect transistor structure includes a low-k spacer layer between metallic interconnects, wherein the low-k spacer layer includes boron nitride nanotubes. In addition, a method for reducing RC delay in an integrated circuit includes forming a component of the integrated circuit from boron nitride nanotubes.

A semiconductor device includes a gate structure on a substrate, a contact etch stop layer (CESL) on the gate structure, an interlayer dielectric (ILD) layer on the CESL, a first contact plug in the ILD layer and adjacent to the gate structure, a first stop layer on the ILD layer, an inter-metal dielectric (IMD) layer on the first stop layer, a first metal interconnection in the IMD layer, and an air gap around the gate structure and exposing the CESL and the first metal interconnection.

Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

An apparatus includes a through-silicon via (TSV) including a conductive material; a first contact plug having an upper surface and a bottom surface directly connected to an upper surface of the TSV; a first wiring directly connected to the upper surface of the first contact plug; a second wiring having an upper surface; a second contact plug having an upper surface and a bottom surface directly connected to the upper surface of the second wiring; and a third wiring directly connected to the upper surface of the second contact plug; wherein the first wiring and the third wiring are in a substantially same level.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.