Disclosed are embodiments of a semiconductor package. The semiconductor package may include: a first substrate; a chip stack on the first substrate, wherein the chip stack comprises one or more semiconductor chips that are stacked to be inclined at a first angle relative to a top surface of the first substrate; a tilt support structure, wherein the tilt support structure is between a first portion of the chip stack and the first substrate; and an anti-slip structure in contact with an end portion of the chip stack.

Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

A method of manufacturing a semiconductor device is provided. A permalloy device is received. An interposer die is formed. A semiconductor die is bonded to the interposer die. A conductive coil is formed over a substrate. The conductive coil includes a bottom metal layer over the substrate, a middle metal layer and a top metal layer interconnected to each other. The permalloy device is disposed over the bottom metal layer through a pick and place operation. An inter-metal-dielectric layer is formed to laterally surround the permalloy device before forming the middle metal layer of the conductive coil. The permalloy device has a polygonal ring shape wrapped with the conductive coil.

A semiconductor package includes a package substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness, and an interposer module mounted on the upper surface layer of the package substrate in the second surface area. The semiconductor package may also include an interposer including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness. The semiconductor package may also include an printed circuit board substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness.

A component carrier includes a stack with electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures have a higher density connection region and a lower density connection region, and a first component and a second component which are surface mounted on the stack. The first component and the second component are electrically coupled with each other by the higher density connection region.

An electronic device includes: a first insulating layer; a first metal bump disposed on the first insulating layer; a second insulating layer disposed on the first metal bump; a metal layer, wherein the first insulating layer is disposed between the second insulating layer and the metal layer; a second metal bump disposed between the metal layer and the first insulating layer, wherein the second metal bump electrically connects to the first metal bump; a third insulating layer disposed between the second metal bump and the first insulating layer, wherein the third insulating layer includes an opening exposing a portion of the second metal bump; and a fourth insulating layer disposed between the third insulating layer and the first insulating layer, wherein a portion of the fourth insulating layer extends and is disposed in the opening to contact the second metal bump.

An optoelectronic package includes a first and a second redistribution layers, a plurality of first and second metal pillars, an optoelectronic chip, a first and a second insulation layers and a processing component. The first metal pillars are disposed on the first redistribution layer. The optoelectronic chip includes a wiring layer, an active structure and a main layer. The wiring layer is electrically connected to the first metal pillars. The main layer is disposed between the wiring layer and the active structure. The first insulation layer disposed on the first redistribution layer covers the optoelectronic chip and the first metal pillars. The processing component is electrically connected to the first redistribution layer which is located between the processing component and the optoelectronic chip. The second metal pillars and the second insulation layer are disposed between the first redistribution layer and the second redistribution layer.

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

A display panel includes a circuit substrate, pixel structures and a molding layer. The circuit substrate has first pad structures and second pad structures. The pixel structures are disposed above a display region of the circuit substrate. Each of at least a portion of the pixel structures includes a first light emitting diode, a first conductive block, and a first conductive connection structure. The first light emitting diode is disposed on a corresponding first pad structure. The first conductive block is disposed on a corresponding second pad structure. The first conductive connection structure electrically connects the first light emitting diode to the first conductive block. The molding layer is located above the circuit substrate and surrounds the first light emitting diode and the first conductive block. The first conductive connection structure is located on the molding layer.

A semiconductor package component which has an outer profile including an oblique package edge obliquely interconnecting between two adjacent side walls. The semiconductor package component includes a first redistribution layer (RDL) unit, a chip unit, a dummy die unit, an encapsulation layer, and a second RDL unit. The chip unit is disposed on the first RDL unit. The dummy die unit includes a dummy die that is disposed on the first RDL unit, and has a dummy die edge which extends in a direction parallel to the oblique package edge. A method for making the semiconductor package component is also disclosed.