An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillars that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillars are conductive wires. A package body encapsulates the electronic component and the conductive pillars. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent to the package body, which is electrically connected to the conductive pillars. In one embodiment, the electrical connection is made through the package body. In another embodiment, the electrical connection is made through the substrate.

A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

Conventional technology cannot provide a conductive pillar module for semiconductor manufacturing that can be used for secondary wiring to a substrate of a flip chip package or for forming a redistribution layer (RDL) in a chip-last (RDL-first) package without using lithography techniques. Provided herein is a conductive pillar module precursor for semiconductor manufacturing, a semiconductor, or semiconductor precursor which has a structure in which a conductive pillar member is supported by a sheet-like cured resin material and provides sufficient adhesion to a substrate, stress relaxation properties, and durability, as well as a manufacturing method thereof.

A semiconductor package includes: a substrate; a chip stack on the substrate; a first interface, in a first region of the substrate and having a first circuit layer; a second interface, in a second region of the substrate and having a second circuit layer, and the chip stack between the first and second interface; a first bonding wire, connected to a first chip and having a first contact point; a second bonding wire, connected to a second chip and having a second contact point; an encapsulation layer, surrounding the chip stack, the first and second interface, the first and second bonding wire on the substrate, and exposing the first and second contact point, and the first and second circuit layer; and a redistribution layer, on the encapsulation layer and connecting the first contact point and the second contact point to the first circuit layer and the second circuit layer.

A method of manufacturing a device includes forming a conductive film on a second surface of a substrate having a first surface and the second surface opposite to the first surface by using a non-superconducting material, forming a through hole penetrating the substrate by etching the substrate from the first surface after forming the conductive film, forming a through electrode in the through hole by using a superconducting material by an electroplating method using the conductive film exposed in the through hole as a seed layer, and removing the conductive film after forming the through electrode.

A semiconductor package may include a redistribution structure, a semiconductor chip on a surface of the redistribution structure, a UBM pad on an opposite surface of the redistribution structure, a barrier pattern on at least a portion of a lower surface of the UBM pad and surrounding a side surface of the UBM pad, and a connection bump on the lower surface of the UBM pad.

A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a first semiconductor device mounted on the redistribution structure, vertical connection conductors on the redistribution structure and apart from the first semiconductor device in a horizontal direction, a second semiconductor device mounted on the vertical connection conductors, and a heat-dissipation plate mounted on the first semiconductor device, wherein the heat-dissipation plate includes a main body and a plurality of protrusions protruding from the main body in the horizontal direction.

A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.

Semiconductor packages, and methods for manufacturing semiconductor packages are provided. In one aspect, a method of manufacturing a semiconductor package includes stacking a plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, the first semiconductor ship being offset from the second semiconductor ship to expose upper connection pads; forming a multilayered photoresist film to cover the plurality of semiconductor chips; forming a plurality of openings by exposing and developing the multilayered photoresist film; forming a plurality of conductive posts by filling the plurality of openings with a conductive material; removing the multilayered photoresist film; forming a molding encapsulant to surround the plurality of semiconductor chips and the plurality of conductive posts; and forming a wiring structure electrically connected to the plurality of conductive posts. The multilayered photoresist film comprises at least two layers having different chemical resistances and resolutions.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.