This invention provides opportunity for diamond and bi-wafer microstructures to be implemented in advanced ICs and advanced IC packages to form a new breed of ICs and SiPs that go beyond the limitations of silicon at the forefront of IC advancement due primarily to diamond's extreme heat dissipating ability. Establishing the diamond and bi-wafer microstructure capabilities and implementing them in advanced ICs and advanced IC packages gives IC and package architects and designers an extra degree of design freedom in achieving extreme IC performance, particularly when thermal management presents a challenge. Diamond's extreme heat spreading ability can be used to dissipate hotspots in processors and other high-power chips such as GaN HEMT, resulting in performance and reliability enhancement for IC and package applications covering HPC, AI, photonics, 5G RF/mmWave, power and IoT, and at the system level propelling the migration from traditional computing to near-memory computing and in-memory computing.

Many electronic devices generate significant amounts of heat during operation, especially those configured for high-performance computing often used to support machine learning/artificial intelligence (ML/AI) applications. However, operating electronic devices at increased temperatures can negatively impact their performance. While it is now common for integrated circuit packages to include a lid that can be coupled to a cooling plate providing heat dissipation, the lid is currently fabricated from copper metal which limits thermal conductivity and thus the ability to provide heat dissipation for the underlying integrated circuit. The present disclosure provide a diamond-based lid for an integrated circuit package, which can provide higher thermal conductivity than the existing copper lids.

A semiconductor device includes a substrate having a first surface, a second surface, and an opening; a semiconductor device layer having a third surface and a fourth surface; a heat transfer member; source electrodes disposed on a fourth surface; and electrically conductive vias that penetrate the semiconductor device layer and a diamond layer to electrically connect the source electrodes to a metal layer. The heat transfer member includes the diamond layer and the metal layer, the diamond layer covers a bottom surface and an inner wall surface of the opening, and the metal layer is disposed on the diamond layer.

The present invention discloses an elastic heat spreader for chip packaging, a packaging structure and a packaging method. The heat spreader includes a top cover plate and a side cover plate that extends outward along an edge of the top cover plate, wherein the top cover plate is configured to be placed on a chip, and at least a partial region of the side cover plate is an elastic member; and the elastic member at least enables the side cover plate to be telescopic in a direction perpendicular to the top cover plate. According to the present invention, a following problem is solved: delamination between the heat spreader and a substrate as well as the chip due to stress generated by different thermal expansion coefficients of the substrate, the heat spreader and the chip in a packaging process of a large-size product.

A device package and heatsink assembly includes a device package containing one or more logic elements and one or more other integrated circuit devices mounted to a package substrate and one or more heatsinks. The other integrated circuit devices are higher above the package substrate's surface than the logic elements. Each heatsink contains chambers for a fluid heat transfer medium. A surface of the logic elements is thermally coupled to the fluid. A semiconductor chip package fabrication method includes bonding a diamond-containing dielet to a semiconductor logic die to form a logic die structure; mounting the logic die structure to a package substrate with the logic die sandwiched between the dielet and the substrate, exposing a surface of the dielet; and mounting one or more other integrated circuit devices to the package substrate. The other integrated circuit devices are higher above the package substrate's surface than the logic die structure.

A reconstituted wafer product includes diamond dies sandwiched between a first wafer and a second wafer in a manner that provides a thermally conductive connection between the first wafer and second wafer through the diamond dies. At least one of the first wafer and second wafer includes pockets containing one or more diamond dies. An alternative reconstituted wafer product may include diamond dies attached to a silicon wafer in a manner that provides a thermally conductive connection between the wafer and the diamond dies, wherein the silicon wafer is bonded to the dies in areas that include one or more areas of recrystallized silicon.

A reconstituted wafer product may include dies containing diamond sandwiched between first and second wafers in a manner that provides a thermally conductive connection between the first wafer and second wafer through the dies containing diamond. Alternatively, dies containing diamond may be attached to a tape in frame or temporary carrier substrate or tape on reel carrier substrate. Alternatively, dies containing diamond may be attached to a wafer in a manner that provides a thermally conductive connection between the wafer and the dies containing diamond. A first smoothening layer may be formed on a first side of the dies between the wafer and the dies. A second smoothening layer may be formed on a second side of the dies with the dies containing sandwiched between the first and second smoothening layers.

A low thermal resistance device package and heatsink assembly may include a device package containing one or more logic elements with the logic elements thermally connected to one or more diamond dies in a manner that provides a thermally conductive connection between the logic elements through the one or more diamond dies and one or more heatsinks. Each heatsink contains one or more chambers configured for a fluid heat transfer medium. A reconstituted wafer product may include a plurality of diamond dies attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond. The first wafer may be a 300 millimeters sized wafer and the diamond dies may include four sector dies arranged in four sectors of the 300 millimeters sized wafer.

A reconstituted wafer product may include a plurality of die structures bonded to a wafer in a manner that provides a thermally conductive connection between the wafer and the plurality of die structures. The wafer is compatible with semiconductor processing. Each die structure may include a die containing diamond bonded to a heatsink-side surface of the wafer. Two or more dies containing diamond in the plurality of die structures are of different thickness.

There is provided a laminated substrate including a three-layer structure composed of: a device substrate, which is composed of at least one single crystal material selected from the group consisting of Si, SiC, GaN, AlN, BN, Ga.sub.2O.sub.3, Cr.sub.2O.sub.3, LiTaO.sub.3, and LiNbO.sub.3; a metal layer on the device substrate; and a diamond layer on the metal layer.