The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a semiconductor substrate; a collector region over the semiconductor substrate; an intrinsic base over the collector region; an electrically insulating heat dissipative material at a junction of the collector region and the intrinsic base; an extrinsic base over the intrinsic base; and an emitter region adjacent to the extrinsic base.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die and a third die, the second die and the third die having a first surface and an opposing second surface, wherein the first surfaces of the second die and the third die are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second die and the third die, the first material having a non-planar surface; and a layer on and in physical contact with the non-planar surface of the first material and with the second surfaces of the second die and the third die, the layer including a second material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K).

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die having a first surface and an opposing second surface, where the first surface of the second die is electrically coupled to the first die by interconnects and the first surface of the third die is electrically coupled to the first die by a bonding material, and the bonding material includes titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; a first material, around the second die and the third die, having a non-planar surface; and a second material, on the non-planar surface of the first material and on the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns.

A composite substrate containing thermally conductive materials is provided. The composite substrate includes a glass base, a first RDL, a second RDL and a thermal dissipation layer. The glass base has a first surface, a second surface opposite to the first surface and a through glass via (TGV) extending to the second surface from the first surface. The first RDL is disposed adjacent to the first surface of the glass base or the thermal dissipation layer. The second RDL is disposed adjacent to the second surface of the glass base. The thermal dissipation layer is disposed on the glass base, having a through thermal via (TTV) extending to the TGV.

A method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein each diamond block has a dimension smaller than the predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; or attaching the first diamond composite wafer to a second semiconductor substrate with the predetermined diameter to form the second diamond composite wafer, or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.

Embodiments of this application provide a semiconductor structure, an electronic device, and a manufacture method for a semiconductor structure, and relate to the field of heat dissipation technologies for electronic products. An example semiconductor structure includes a semiconductor device, a bonding layer, a substrate, a conducting via, and a metal layer. The semiconductor device is disposed on an upper surface of the substrate by using the bonding layer. The metal layer is disposed on a lower surface of the substrate. The substrate includes a base plate, a groove formed on the base plate, and a diamond accommodated in the groove. The conducting via penetrates the substrate, the bonding layer, and at least a part of the semiconductor device, and is electrically connected to the metal layer. The groove bypasses the conducting via.

An integrated circuit (IC) assembly may include stacked IC die and a respective interposer between adjacent ones of the stacked die. Each interposer may include an interposer bottom and an interposer top coupled thereto and defining a heat exchange fluid chamber therebetween. Each interposer may also include interposer dielectric pillars extending within the heat exchange fluid chamber between the interposer bottom and the interposer top, and a heat exchange fluid within the heat exchange fluid chamber. Each interposer may also include a wick structure within the heat exchange fluid chamber for moving the heat exchange fluid in a liquid phase into the heat exchange fluid chamber, and electrically conductive through-vias extending within respective ones of the interposer dielectric pillars and being exposed on outer surfaces of the interposer bottom and the interposer top.

Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.

An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein to reduce the coefficient of thermal expansion thereof. The filler material may be a plurality of graphitic carbon filler particles, wherein the plurality of graphitic carbon filler particles has an average aspect ratio of greater than about 10, or the filler material may be a plurality of diamond particles, wherein the filler material is clad with a metal material.