An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

A semiconductor package structure includes a redistribution structure layer, at least one chip, an encapsulant, and multiple solder balls. The redistribution structure layer includes multiple first connectors located on a first side. Each first connector includes a connecting pad, a soldering pad, and multiple conductive blind holes located between the connecting pad and the soldering pad. The conductive blind holes are disposed separately from each other and connect the connecting pad and the soldering pad. The chip is disposed on a second side of the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the second side and at least covers the chip and the second side. The solder balls are disposed on the first side of the redistribution structure layer and electrically connected to the redistribution structure layer. The solder balls are respectively connected to the connecting pad of each first connector.

A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A semiconductor package may include a first substrate, semiconductor dies stacked on the first substrate in a direction perpendicular to a top surface of the first substrate to have a stepwise structure, a mold layer disposed on the first substrate to cover the semiconductor dies, a second substrate disposed on the mold layer, and vertical conductive lines electrically connecting the semiconductor dies to the second substrate. The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.

A package for a semiconductor device includes a metal base plate, a wall portion, a first metal film, and a lead portion. The base plate has a first region and a second region surrounding the first region. The wall portion has a first frame body comprising metal and a second frame body comprising resin. The first frame body is provided on the second region. The second frame body is provided on the first frame body. The first metal film is provided on the second frame body. The lead portion is conductively bonded to the first metal film. The first frame body is conductively bonded to the base plate. A thickness of the first frame body in a first direction that is a direction in which the first frame body and the second frame body are arranged is larger than a thickness of the first metal film in the first direction.

A printed circuit board including: a conductive pattern including a seed metal layer and a pattern metal layer disposed on the seed metal layer, and the seed metal layer includes a first metal layer including a first metal, and a second metal layer disposed on the first metal layer and connected to the pattern metal layer and including a second metal, the first metal layer has a thickness thicker than the second metal layer, and the first metal is one selected from the group consisting of aluminum (Al), iridium (Ir), molybdenum (Mo), tungsten (W), cobalt (Co), nickel (Ni), and ruthenium (Ru).

An electronic package is provided. The electronic package comprises a substrate having a first side and a second side, the substrate configured to receive one or more electronic components; a first electronic component mounted to the first side of the substrate; a first mold structure extending over at least part of the first side of the substrate; a group of through-mold connections provided on the first side of the substrate, the through-mold connections substantially formed of non-reflowable electrically conductive material; the first mold structure substantially encapsulating the group of through-mold connections; the group of through-mold connections exposed through the first mold structure. An electronic device comprising such an electronic package is also provided. A method of manufacturing such an electronic package is also provided.

A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a first dielectric layer, at least one antenna, at least one die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive circuits, a third dielectric layer, a plurality of second conductive circuits, and an outer protective layer is provided. The first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. The die is electrically connected with the antenna. The die is electrically connected to the outside through bonding pads around a chip area on a second surface of the die. Thereby the FOWLP unit is formed and problems of the FOWLP module or technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and a first integrated circuit chip on the interposer. The interposer includes a galvanic effect test structure including a test contact pad and a detection contact pad. The interposer includes a plurality of primary contact pads electrically coupled to the first integrated circuit chip. The galvanic effect structure can be utilized to test the interposer for galvanic corrosion prior to assembling the interposer into the integrated circuit package.