A fan-out wafer level packaging (FOWLP) unit which includes a substrate, at least one die, a first dielectric layer, at least one conductive pillar, a second dielectric layer, a plurality of first conductive circuits, a first outer protective layer, a third dielectric layer, a plurality of second conductive circuits, and a second outer protective layer is provided. The die is electrically connected with the outside through at least one first bonding pad around a chip area on a second surface of the die. The die is further electrically connected with the outside through a second bonding pad in at least one opening of the second outer protective layer. Both the first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. Thereby problems of conventional FOWLP technology including higher manufacturing cost and less environmental benefit can be solved.

A method of manufacturing a semiconductor device is provided. A permalloy device is received. An interposer die is formed. A semiconductor die is bonded to the interposer die. A conductive coil is formed over a substrate. The conductive coil includes a bottom metal layer over the substrate, a middle metal layer and a top metal layer interconnected to each other. The permalloy device is disposed over the bottom metal layer through a pick and place operation. An inter-metal-dielectric layer is formed to laterally surround the permalloy device before forming the middle metal layer of the conductive coil. The permalloy device has a polygonal ring shape wrapped with the conductive coil.

A light-emitting substrate and a backlight module are provided, the light-emitting substrate includes a base substrate; a metal wiring layer; a first planarization layer; an electrode layer; the electrode layer including a metal sub-layer and a conductive sub-layer stacked; material of the metal sub-layer include metal or metal alloy; the conductive sub-layer covers the metal sub-layer; a second planarization layer at a side of the electrode layer a functional device layer at a side of the second planarization layer and including a plurality of functional devices electrically connected to the electrode layer; the electrode layer includes a first buffer metal layer between the metal sub-layer and the conductive sub-layer; material of the first buffer metal layer is any one of or a mixture of more than one of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy and molybdenum-magnesium-aluminum alloy.

The present disclosure relates to a semiconductor package. An embodiment of the present disclosure provides a semiconductor package including: a package substrate; a semiconductor chip positioned on a first surface of the package substrate; a pad positioned on a second surface of the package substrate; a solder resist layer including an opening positioned on the second surface of the package substrate and the pad, the solder resist layer vertically overlapping at least a portion of the pad, the solder resist layer including a dummy opening spaced apart from the opening; and a filling layer positioned within the dummy opening, wherein the dummy opening is positioned farther than the opening from a center of the package substrate in a plan view.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

A memory module, includes a module substrate and at least one semiconductor package on the module substrate that includes a package substrate having a lower surface and an upper surface. First and second groups of lower pads are on the lower surface, and upper pads are on the upper surface and are electrically connected to the lower pads of the first group. A chip structure is on the upper surface of the package substrate and is electrically connected to the upper pads. First connection bumps connect the lower pads of the first group to the module substrate, and second connection bumps connect the lower pads of the second group to the module substrate. The first connection bumps have a first maximum width at a first distance from the package substrate, and the second connection bumps have a second maximum width at a second, shorter distance from the package substrate.

According to the present disclosure, a packaging substrate includes a glass core and an adhesion reinforcement layer disposed on the glass core. The adhesion reinforcement layer includes a first adhesion reinforcement layer and a second adhesion reinforcement layer disposed on the first adhesion reinforcement layer. The first adhesion reinforcement layer includes a transition metal and silicon. The second adhesion reinforcement layer includes a transition metal. In such a case, it is possible to improve the bonding strength of the conductive layer with respect to the glass core, while effectively suppressing damage to the packaging substrate caused by the difference in thermal expansion properties between the glass core and the conductive layer.

In a first insulating layer, a through-hole penetrates the first insulating layer in the thickness direction. A first conductor pattern is on a first surface that is one surface of the first insulating layer. The first conductor pattern closes the opening of the through-hole on the side of the first surface. A first connection conductor is in the through-hole. The first connection conductor is connected to the first conductor pattern, and the dimension of the first connection conductor in the thickness direction is smaller than the dimension of the first insulating layer in the thickness direction. A metal element with the maximum content in the first conductor pattern is the same as a metal element with the maximum content in the first connection conductor.

A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.

A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.