A method of manufacturing a power semiconductor device in accordance with an embodiment of the present disclosure may include providing a substrate disposed atop a heatsink, electrically connecting a semiconductor die to a top surface of the substrate, disposing a thin metallic layer atop the substrate, disposing a terminal atop the thin metallic layer, and performing a welding operation wherein a laser beam is directed at a top surface of the terminal to produce a plurality of weld connections connecting the terminal to the substrate, wherein the weld connections are separated by gaps, and wherein heat generated during the welding operation melts the thin metallic layer and molten material of the thin metallic flows into the gaps.

Semiconductor devices including the use of solder materials and methods of manufacturing are provided. In embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. By utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.

A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.

A packaging device is provided. The packaging device includes a die disposed over a laminate, the die comprising a first via structure, and an interposer disposed between the die and the laminate. The interposer includes a second via structure. The packaging device also includes a lid disposed over the interposer and covering the die, a first patterned conductive layer disposed between the die and the interposer, and between the lid and the interposer; and a second patterned conductive layer disposed between the laminate and the interposer. The first patterned conductive layer includes a bonding structure electrically and thermally connected to the first via structure and the second via structure.

A semiconductor package includes a package substrate having bond fingers, at least one semiconductor chip on the package substrate, the at least one semiconductor chip having chip pads on an upper surface thereof, and conductive wires electrically connecting the chip pads and the bond fingers, wherein the package substrate includes an insulating layer having an upper surface and a lower surface opposite the upper surface, the insulating layer having a recess of a predetermined depth from the upper surface of the insulating layer, upper circuit wirings having pad patterns in the insulating layer and extending such that at least a portion of each of the pad patterns is exposed from a bottom surface of the recess, and a respective plating pattern on the portion of each of the pad patterns that is exposed, the respective plating pattern provided as the bond finger.

A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.

A semiconductor package includes a lower redistribution structure; a connection structure on the lower redistribution structure and defining a cavity; a semiconductor chip on the lower redistribution structure and in the cavity; and an upper redistribution structure above the connection structure and the semiconductor chip and electrically connected to the connection structure, wherein the upper redistribution structure includes an upper insulating layer and an upper redistribution pattern; an upper connection pad on a top surface of the upper insulating layer, the upper connection pad being electrically connected to the upper redistribution pattern, including a horizontal portion and a vertical portion, and having a bowl shape; a metal pad on the horizontal portion and apart from an inner side surface of the vertical portion; and an upper passivation layer on the top surface of the upper insulating layer and defining an opening exposing a portion of the metal pad.

A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first sidewall and a second portion that includes a second sidewall, wherein the first sidewall includes seed metallization and the second sidewall excludes the seed metallization.

Microelectronic assembly architectures including a die stack in which each die includes a redistribution layer, and the die stack is positioned such that the face of each die is perpendicular to a face of a base, are provided. Each die has a first face and a second face opposite the first face, and an edge extending between the first and second faces. A redistribution layer is deposited on the first face of each die. The faces of each die in the die stack are parallel to the faces of the other dies. The die stack is positioned on the base such that the faces of each die are orthogonal to the face of the base. Each die can have a conductive contact on a bottom edge, and the conductive contact can be coupled to the respective redistribution layer on the die and to a conductive contact on the base.