An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

A semiconductor chip includes: a photonic integrated circuit (PIC) comprising an active component electrically connected to a first landing pad at a surface of the PIC, wherein the first landing pad is configured to receive a copper pillar, which, when installed, provides at least a portion of a first electrical interconnect between the active photonic component and a second integrated circuit to be stacked on the surface of the PIC, and wherein, when viewed from above the PIC towards the PIC, a center of the active photonic component on the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m.

Exemplary semiconductor structures may include a substrate defining a device layer. The structures may include a first deep-trench-capacitor (DTC) coupled to a first surface of the substrate. The structures may include a second DTC coupled to a second surface of the substrate opposite the first surface of the substrate.

A solid state circuit breaker structure and electronic switching circuit is provided. The solid state circuit breaker structure includes a power substrate, a power die, a plurality of bond wires, and a magnetic body. The power die is mounted on the power substrate. The bond wires extend outwardly from the power die. The magnetic body is attached to the power substrate and disposed to increase a magnetic field produced by a current flowing through the bond wires and thereby produce a first inductance that produces a decrease in an overvoltage at turn off of the power die.

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m; and electrically connecting the first landing pad to one of the two electrodes.

According to one embodiment, an isolator includes first and second electrodes, first and second insulating portions, and a first dielectric portion. The first insulating portion is provided on the first electrode. The second electrode is provided on the first insulating portion. The second insulating portion is provided around the second electrode along a first plane perpendicular to a first direction. The second insulating portion contacts the second electrode. The first dielectric portion is provided between the first and second insulating portions. At least a portion of the first dielectric portion contacts the second electrode and is positioned around the second electrode along the first plane. A distance between a lower end of the second electrode and a first interface between the first dielectric portion and the second insulating portion is less than a distance between the first interface and an upper end of the second electrode.

A method of manufacturing a semiconductor device is provided. A permalloy device is received. An interposer die is formed. A semiconductor die is bonded to the interposer die. A conductive coil is formed over a substrate. The conductive coil includes a bottom metal layer over the substrate, a middle metal layer and a top metal layer interconnected to each other. The permalloy device is disposed over the bottom metal layer through a pick and place operation. An inter-metal-dielectric layer is formed to laterally surround the permalloy device before forming the middle metal layer of the conductive coil. The permalloy device has a polygonal ring shape wrapped with the conductive coil.

Disclosed are power modules with vertically-oriented power dies. A power die includes a power transistor. A plane of the power die is oriented vertically relative to a plane of a motherboard or other substrate. An inductor is disposed on a top end of the power module or between two power dies in the power module.

A power module includes: a first substrate having an outer surface and an inner surface; a semiconductor die coupled to the inner surface of the first substrate; a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate; and a flex circuit coupled to the semiconductor die.

A semiconductor module, including: a first circuit board and a second circuit board respectively have a first switching element and a second switching element located thereon, each of the first and second switching elements having an emitter electrode; a first connecting portion and a second connecting portion respectively electrically connected to the emitter electrodes of the first and second switching elements over the first and second circuit boards; an auxiliary emitter terminal; and an auxiliary emitter wiring electrically connected to the auxiliary emitter terminal. The auxiliary emitter wiring includes: a branch point, a common wiring portion which connects the auxiliary emitter terminal and the branch point, and a first discrete wiring portion and a second discrete wiring portion which connect the branch point respectively to the first and second connecting portions, and which each have an inductance smaller than 10 percent of an inductance of the common wiring portion.