In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.

In a power semiconductor module including a snubber capacitor, the power semiconductor module capable of achieving both a high current density and prevention of heating of the snubber capacitor is provided. The power semiconductor module includes: a positive electrode terminal; a negative electrode terminal of which at least a part is disposed to overlap the positive electrode terminal in a plan view; a first wiring branching from the positive electrode terminal; a second wiring branching from the negative electrode terminal; and a snubber capacitor disposed outside of a position at which the positive electrode terminal and the negative terminal overlap each other in the plan view and connected through the first wiring and the second wiring.

A power module includes a insulation substrate, a first and a second input terminal supported by the insulation substrate, a plurality of arm circuits provided on the insulation substrate, and a plurality of output terminals corresponding to the plurality of arm circuits. The arm circuits each include a part of a wiring pattern formed on the insulation substrate, and a first switching element and a second switching element mutually connected in series via the part of the wiring pattern. The output terminals are each connected to a connection point between the first switching element and the second switching element in a corresponding one of the plurality of arm circuits. The plurality of arm circuits are located so as to overlap with a circle surrounding the first input terminal, as viewed in a thickness direction the insulation substrate.

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

Disclosed are techniques for a structure of an inductive device. In an aspect, an inductive device includes a first set of conductive patterns and a second set of conductive patterns alternatively arranged in a first array; a third set of conductive patterns and a fourth set of conductive patterns alternatively arranged in a second array; a first set of conductive structures configured to connect the first set of conductive patterns and the third set of conductive patterns to form a first coil structure; a second set of conductive structures configured to connect the second set of conductive patterns and the fourth set of conductive patterns to form a second coil structure; and a interconnect configured to connect a first conductive structure of the first set of conductive structures to a second conductive structure of the second set of conductive structures.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

A power semiconductor module includes a flexible first substrate and a flexible second substrate and a first and second power semiconductor switch arranged between the first and second substrate. The first substrate has an electrically conductive first metal layer facing towards the power semiconductor switches, an electrically conductive second metal layer and an electrically non-conductive first insulation film arranged between the first and second metal layer. The second substrate has an electrically non-conductive second insulation film and a third metal layer arranged on the second insulation film. The first and second power semiconductor switch are electrically interconnected by the first and second substrate to form a half-bridge circuit.

A semiconductor device is provided. The semiconductor device includes a first port, a second port, a first inductor, a second inductor and a switch circuit. The first inductor is coupled between a first port and a second port. The first inductor includes a first strip part close to the first port. The second inductor and the switch circuit are connected in series. The series connected second inductor and the switch circuit are coupled between the first port and the second port and overlap the first inductor. The second inductor includes at least one first vertical portion that overlaps and is perpendicular to the first strip part.

An IC module according to the present invention includes a rectangular substrate having long sides extending in a first direction; a connection coil formed in a spiral shape on a first surface of the substrate; an outermost connection terminal portion formed at an outermost end of the connection coil; and an IC chip provided on a portion of the first surface on an inner peripheral side relative to the connection coil, wherein the outermost connection terminal portion includes an outermost through-hole portion penetrating the substrate in a thickness direction of the substrate, and an outermost land portion surrounding the outermost through-hole portion and connecting between the outermost through-hole portion and the connection coil; and as viewed in a second direction perpendicular to both the first direction and the thickness direction, the outermost connection terminal portion is disposed on a first side in the first direction relative to the IC chip.