H10P72/0421

Multi-flow gas circuits, processing chambers, and related apparatus and methods for semiconductor manufacturing

Embodiments of the present disclosure relate to multi-flow gas circuits, processing chambers, and related apparatus and methods applicable for semiconductor manufacturing. In one or more embodiments, a processing chamber includes a chamber body, one or more heat sources, and a gas circuit in fluid communication with the chamber body. The gas circuit includes a first flow controller and a first set of valves in fluid communication with the first flow controller. The first set of valves are in fluid communication with a first set of inject passages. The gas circuit includes a second flow controller and a second set of valves in fluid communication with the second flow controller. The second set of valves is in fluid communication with a second set of inject passages. The second set of inject passages and the first set of inject passages alternate with respect to each other along the plurality of flow levels.

METHOD OF SUSTAINING PLASMA FOR PLASMA PROCESSING

A method for plasma processing a substrate includes: sustaining a plasma in a plasma processing chamber, the plasma processing chamber including a first electrode and a second electrode, where sustaining the plasma includes: coupling a source signal to the first electrode; and applying a bias signal to the second electrode, the bias signal having a spike waveform including a plurality of bias pulses, each of the bias pulses including a DC base voltage for a base duration and a triangular voltage spike having a rise time from the base voltage to a peak voltage and a fall time from the peak voltage to the base voltage, a sum of the rise time, the fall time, and the base duration including a pulse period, the applying including: independently adjusting the rise time and fall time to obtain a narrow energy spread of a mode at a high modal energy in an ion energy distribution function (IEDF) of an ion flux incident on the substrate, the narrow energy spread including a first width of the high energy mode of the IEDF that is smaller than a second width of the high energy mode of the IEDF obtainable using a rectangular pulse waveform.

Atomic Layer Process Chamber for Optimal Etching and Deposition with Controlled Ion and Radical Exposure
20260066245 · 2026-03-05 · ·

A plasma process chamber, divided into upper and lower sections by a grounded ion filter (GIF), is designed to optimize both ALE and ALD processes. In the ALE process, the substrate in the lower chamber is modified by chemically active neutrals, while ions are blocked by the GIF, enhancing process precision and ideality. During the ALD process, the plasma activation step utilizes radicals without ion interference, improving film conformity, particularly on high aspect ratio structures. This integrated chamber design ensures precise control and optimal conditions for both ALE and ALD, facilitating advanced semiconductor fabrication.

PROCESSING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, PROCESSING APPARATUS, AND RECORDING MEDIUM

There is provided a technique that includes: (a) establishing a state in which a product substrate and a non-product substrate to which a substance M is adsorbed are placed in a processing chamber; and (b) etching a surface of the product substrate by supplying an etching agent into the processing chamber in the state in which the product substrate and the non-product substrate are placed to cause the substance M adsorbed to the non-product substrate to react with the etching agent.

Etching method and etching apparatus

An etching method includes a preparing step and a removing step. In the preparing step, a substrate is prepared which includes a first film, a second film stacked on the first film, and a hard mask stacked on the second film, such that the second film is etched with the hard mask having a formed pattern as a mask until the first film is exposed. In the removing step, the hard mask is removed using a fluorine-containing gas. Further, the removing step is executed for a time longer than a first time from a start of a supply of the fluorine-containing gas to a start of an etching of the hard mask, and shorter than a second time from the start of the supply of the fluorine-containing gas to a start of an etching of the first film.

Liquid source vaporization apparatus, control method for a liquid source vaporization apparatus and program recording medium on which is recorded a program for a liquid source vaporization apparatus

There is provided a control valve that is provided on a flow path along which flows a source fluid which is a liquid source or a source gas obtained by vaporizing a liquid source, a pressure sensor that is provided on a downstream side of the control valve, a flow rate sensor that measures a flow rate of the source fluid, and a valve controller that, while reducing a deviation between a set pressure and a measured pressure measured by the pressure sensor, controls the control valve such that a measured flow rate measured by the flow rate sensor is equal to or less than a limit flow rate which is a flow rate that is set based on an upper limit flow rate at which the liquid source can still be vaporized.

Semiconductor processing chamber adapter

Exemplary semiconductor processing systems may include a processing chamber. The systems may include a remote plasma unit coupled with the processing chamber. The systems may include an adapter coupled between the remote plasma unit and the processing chamber. The adapter may be characterized by a first end and a second end opposite the first end. The remote plasma unit may be coupled with the adapter at the first end. The adapter may define a first central channel extending more than 50% of a length of the adapter from the first end of the adapter. The adapter may define a second central channel extending less than 50% of the length of the adapter from the second end of the adapter. The adapter may define a transition between the first central channel and the second central channel.

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

A substrate processing apparatus includes: a substrate holder configured to hold a substrate; a shower head including a first hollow portion, a first slit coupled to the first hollow portion and extending in a first direction, a second slit coupled to the first slit and extending in a second direction intersecting the first direction and a third direction intersecting the first and second directions, a third slit coupled to the second slit and extending in the first direction, and a plurality of first gas ejection holes coupled to the first hollow portion, the shower head facing the substrate holder; a pipe structure including a first pipe coupled to the third slit; and a gas supplier connected to the first pipe and configured to supply a gas to the substrate from the plurality of first gas ejection holes.

SEMICONDUCTOR REACTION CHAMBER AND SEMICONDUCTOR PROCESSING APPARATUS AND METHODS
20260076135 · 2026-03-12 ·

A method for a semiconductor reaction chamber includes monitoring a first pressure in an inner chamber, monitoring a second pressure in an accommodation chamber, and in response to detection of a pressure difference between the first pressure and the second pressure greater than a threshold value, balancing the first pressure and the second pressure. The inner chamber is arranged for processing a workpiece. An electrostatic chuck is disposed in the inner chamber for placing the workpiece and includes a functional layer and a base body. The functional layer is fixed on the base body. The accommodation chamber is arranged under the functional layer and enclosed by the functional layer and the base body. A functional wire is disposed in the accommodation chamber and connected with the functional layer. The accommodation chamber is isolated from the inner chamber.

METHOD FOR ETCHING FEATURES IN A STACK
20260076118 · 2026-03-12 ·

A method for etching features in a stack comprising a silicon oxide layer below a mask is provided. A substrate support for supporting the stack in an etch chamber is cooled to a temperature below 0 C. An etch gas comprising a halogen containing component and a phosphorous containing component is provided. A plasma is generated from the etch gas. A bias is provided to accelerate ions from the plasma to the stack. Features are selectively etched in the stack with respect to the mask.