In one example, an electronic device comprises a substrate comprising a conductive structure and a dielectric structure, the dielectric structure comprising an upper dielectric layer, an electronic component over a top side of the substrate and coupled with the conductive structure, an encapsulant over the top side of the substrate and adjacent a lateral side of the electronic component, and a shield over the top side of the electronic component and contacting a lateral side of the encapsulant and a first lateral side of the substrate. The conductive structure comprises a first tab structure at the first lateral side of the substrate, and wherein the first tab structure contacts the shield and extends above the upper dielectric layer. Other examples and related methods are also disclosed herein.

In one example, a semiconductor structure or device comprises a substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure, an electronic component on the top side of the conductive structure, a package body on the top side of the conductive structure and contacting a side of the electronic component, a shield on a top side of the package body and a lateral side of the package body, and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.

Provided is a package structure, including a substrate, a chip on the substrate in a flip-chip manner, the chip including a circuit layer, and a side heat dissipator on a side of the chip, the side heat dissipator comprising a heat conduction material, wherein the side heat dissipator is electrically connected to the circuit layer.

A display device includes: a display panel; a driving integrated circuit chip configured to drive the display panel; a first printed circuit board connected to the display panel; a second printed circuit board connected to the first printed circuit board; and a cover including a body portion covering the driving integrated circuit chip, the first printed circuit board, and the second printed circuit board, and a wing portion protruding from the body portion, wherein the wing portion extends from a front surface of the display panel to a rear surface of the display panel while surrounding a side surface of the display panel.

A semiconductor package of an embodiment includes: a wiring substrate having a first surface and a second surface on a side opposite to the first surface; at least one semiconductor chip provided in plurality at different heights from the first surface in a vertical direction; a sealing resin covering the first surface of the wiring substrate and surfaces of the at least one semiconductor chip; a layer formed over a top layer of the at least one semiconductor chip; and an external terminal provided on the second surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal.

A power semiconductor module includes a power semiconductor element having a first electrode, a second electrode, and a control electrode. The power semiconductor element is configured to selectively control a conductivity state between the first electrode and the second electrode. The power semiconductor module further includes a first power line electrically connected to the first electrode, a second power line electrically connected to the second electrode, a first control line electrically connected to the control electrode, a second control line electrically connected to the second electrode, and a heat sink having a front surface on which the power semiconductor element is formed. The heat sink includes a shielding layer. The first control line and the second control line extend through the heat sink.

In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

A system board includes a module board that connects to the system board with an interposer having compressible connectors. The module board can further be covered by a shield that has a metal alloy having an element to provide good electrical conductivity and an element to provide structural integrity and heat transfer. The module board can further include gaskets to interconnect the shield to a ground plane of the module board. the interposer board can further include an extra column of ground connections to reduce signaling noise between the interposer board and the system board.