A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

The present invention addresses the problem of providing a novel SiC epitaxial substrate manufacturing method and manufacturing device therefor. An SiC substrate and an SiC material, which has a lower doping concentration than said SiC substrate, are heated facing one another, and material is transported from the SiC material to the SiC substrate to form an SiC epitaxial layer. As a result, in comparison with the existing method (chemical vapour deposition), it is possible to provide an SiC epitaxial substrate manufacturing method with a reduced number of parameters to be controlled.

A SiC epitaxial wafer according to an embodiment includes a SiC substrate, and a SiC epitaxial layer on one surface of the SiC substrate. The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate, and has an impurity concentration higher than an impurity concentration of the drift layer. The impurity concentration of the buffer layer is 2.010.sup.18 cm.sup.3 or more. In a case where the impurity concentration at a center in plan view in a laminating direction is measured in the laminating direction, uniformity of the impurity concentration in the buffer layer is 50% or less.

Provided are a crack-free laminated film and a structure including this laminated film. This laminated film includes: a buffer layer; and at least one layer of gallium nitride base film disposed on the buffer layer. Moreover, the compression stress of the entire laminated film is 2.0 to 5.0 GPa.

A method for growing a III-V material may include forming at least one layer on a stack including a crystalline layer made of III-V material, a first masking layer surmounting the germination layer, the first masking layer having at least one first opening; depositing a second masking layer covering an upper face of the sacrificial layer; forming at least one second opening in the second masking layer; removing the sacrificial layer selectively at the first masking layer and at the second masking layer; epitaxially growing a material made of the III-V material from the germination layer; forming al least one third opening in the second masking layer; and epitaxially growing at least one material made of the III-V material from the first epitaxial layer.

Disclosed are an MPS diode device and a preparation method therefor. The MPS diode device comprises a plurality of cells arranged in parallel, wherein each cell comprises a cathode electrode, and a substrate, epitaxial layer, buffer layer, and anode electrode that are formed in succession on the cathode electrode; two active regions are formed on the side of the epitaxial layer away from the substrate; the width of forbidden band of the buffer layer is greater than the width of forbidden band of the epitaxial layer, and a material of the buffer layer and a material of the epitaxial layer are allotropes; and first openings are formed at the positions in the buffer layer opposite to the active regions, and an ohmic metal layer is formed in the first openings.

The present disclosure has an object of providing a method of manufacturing a semiconductor device whose manufacturing processes can be simplified. The method of manufacturing the semiconductor device according to the present disclosure includes: a preparation process of preparing two crystalline substrates made of silicon carbide and having respective constant thicknesses; a laminating process of laminating the two crystalline substrates to form a laminated crystalline substrate; an epitaxial growth process of forming an epitaxial layer on a first main surface of the laminated crystalline substrate; an element forming process of forming an element on the epitaxial layer; and a grinding process of grinding, after the element forming process, the laminated crystalline substrate from a second main surface of the laminated crystalline substrate to grind an interface between the laminated two crystalline substrates, the second main surface facing the first main surface.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.010.sup.14 cm.sup.3 at any position in the plane of the epitaxial layer.

An object of the present invention is to provide a novel technique capable of suppressing the occurrence of cracks in the growth layer. The present invention is a method for manufacturing a semiconductor substrate, which includes: an embrittlement processing step S10 of reducing strength of an underlying substrate 10; and a crystal growth step S20 of forming the growth layer 20 on the underlying substrate 10. In addition, the present invention is a method for suppressing the occurrence of cracks in the growth layer 20, and this method includes an embrittlement processing step S10 of reducing the strength of the underlying substrate 10 before forming the growth layer 20 on the underlying substrate 10.