Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

The present disclosure provides a semiconductor structure and a method of forming the semiconductor structure. The semiconductor structure includes a silicon substrate, a first III-V semiconductor layer over the silicon substrate, a second III-V semiconductor layer over the first III-V semiconductor layer, a gate electrode over the second III-V semiconductor layer, and a source electrode and a drain electrode coupled to the second III-V semiconductor layer. A ratio of a thickness of the silicon substrate and a thickness of the first III-V semiconductor layer is between approximately 0.6% and approximately 0.8%.

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

A substrate processing method of processing a substrate having a base film includes a loading process of loading the substrate into a processing container, a first process of performing a first plasma process in a state where the loaded substrate is held at a first position by raising substrate support pins of a stage arranged in the processing container, and a second process of performing a second plasma process while holding the substrate at a second position by lowering the substrate support pins.

Provided is a method for manufacturing a semiconductor silicon wafer capable of inhibiting P-aggregation defects (SiP defects) and SF in an epitaxial layer. The method includes a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500 C. or lower after the step of forming the silicon oxide film, a step of heat treatment where the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100 C. or higher and 1250 C. or lower for 30 minutes or longer and 120 minutes or shorter after the heat treatment, a step of removing surface oxide film formed on the front surface of the substrate, and a step of depositing a silicon monocrystalline epitaxial layer on the substrate after the step of removing the surface oxide film.

Embodiments according to the present invention provide a growth substrate wafer for high-performance GaN switching power devices, comprising: a Si growth substrate; a first AlN nucleation layer formed on the Si growth substrate; and a plurality of SiOx protrusions (Protrusion) discontinuously spaced apart and arranged on the first AlN nucleation layer, wherein the surface of the first AlN nucleation layer is exposed in the regions between the plurality of SiOx protrusions.

An epitaxial wafer includes a silicon substrate having a top surface and an epitaxial layer on said top surface, wherein the epitaxial layer has a thickness in a range of 0.3 m to 1.0 m, and a thickness variation of 1% or less. A method of preparing such epitaxial wafer includes placing a silicon substrate on a susceptor in an epitaxial reactor; rotating the susceptor at a rotation rate (D); and applying a source gas in the epitaxial reactor to grow an epitaxial layer of a desired thickness (B) at a growth rate (A) on the silicon substrate; wherein the source gas is applied for a growth time (C) that satisfies C=B/A and the rotation rate (D) is selected from a range of 22 to 70 rpm that allows the susceptor to rotate to an exact integer number of turns (E) based on a relationship D=E/C.

An epitaxial wafer includes a silicon substrate having an epitaxial layer of 0.3 m to 1.0 m thickness and thickness variation of 1% or less, the thickness variation being a percent difference between thicknesses at any two symmetrical points of the epitaxial layer about 10 mm inward from an outer edge of the epitaxial wafer. A preparation method includes placing a silicon substrate on a susceptor in an epitaxial reactor; rotating the susceptor at a rotation rate (D); and applying a source gas to grow an epitaxial layer of a desired thickness (B) at a growth rate (A). The source gas is applied for a growth time (C) that satisfies C=B/A and the rotation rate (D) is selected from a range of 22 to 70 rpm that allows the susceptor to rotate to an exact integer number of turns (E) based on a relationship D=E/C.