A method of fabricating semiconducting tellurium (Te) nanomesh. The method includes the steps of preparing a substrate, vaporizing Te powders under a first temperature; and growing Te nanomesh on the substrate using the vaporized Te powders under a second temperature. The first temperature is higher than the second temperature. The rationally designed nanomesh exhibits exciting properties, such as micrometer-level patterning capacity, excellent field-effect hole mobility, fast photoresponse in the optical communication region, and controllable electronic structure of the mixed-dimensional heterojunctions.

In a first step S101, a first region in which a polarity inversion layer is formed, and a second region in which the polarity inversion layer is not formed are provided on a substrate. Next, in a second step S102, a first nitride semiconductor is epitaxially grown on the substrate having the first region and the second region along the c-axis direction such that a first semiconductor layer is formed. Next, in a third step S103, a second nitride semiconductor is epitaxially grown on the first semiconductor layer along the c-axis direction such that a second semiconductor layer is formed on the first semiconductor layer. The second nitride semiconductor has different polarization, electron affinity, and band-gap energy from the first nitride semiconductor. The second semiconductor layer forms a heterojunction with the first semiconductor layer. The interface therebetween has a polarization charge, which is positive or negative depending on polarity.

A semiconductor laminate at least including: a base; a buffer layer; and a crystalline metal oxide semiconductor film containing at least one metal element and having a corundum structure, the semiconductor laminate having the buffer layer on a main surface of the base directly or via another layer, the semiconductor laminate having the crystalline metal oxide semiconductor film on the buffer layer. The buffer layer is a laminate structure of a plurality of buffer films each with a different composition, and at least two buffer films of the plurality of buffer films have a film thickness of 200 nm or more and 650 nm or less.

In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 , respectively, so as to realize the flatness of the silicon-on-insulator film.

Disclosed are a semiconductor structure and a method for manufacturing a semiconductor structure, the method includes: forming a first transition layer, a protection layer and an active structure layer sequentially epitaxially on a side of a growth substrate, where a surface, away from the growth substrate, of the first transition layer is a two-dimensional flat surface; on a first plane, an orthographic projection of the active structure layer is at least partially covered by an orthographic projection of the protection layer, and the first plane is perpendicular to an arrangement direction of the protection layer and the active structure layer; detaching the growth substrate by a laser lift-off process, to make the epitaxial layer transferred to a transfer substrate; etching the first transition layer up to the protection layer, to make a surface, away from the active structure layer, of the protection layer to be a planarization surface.