A heat exchanger for a chip package is provided. The heat exchanger includes a body having an upper side, a lower side, and an internal cavity disposed in the body between the upper side and the lower side. A first outlet port and a second outlet port are formed in the body and are in fluid communication with the internal cavity. An inlet port is formed through the upper side of the body between the first and second outlet ports to supply fluid into the internal cavity.

A semiconductor die includes a metalized layer on an upper surface of the semiconductor die and a plurality of metal wires having a defined shape. At least one end of each of the plurality of metal wires is bonded to the metalized layer and an upper portion of each of the plurality of metal wires may extend at least partially in parallel to the metalized layer of the semiconductor die. The plurality of metal wires are arranged in a sequence such that a channel is formed by a space between the metalized layer of the semiconductor die and the upper portion of each of the metal wires that may extend at least partially in parallel to the metalized layer. The upper portion of each of the plurality of metal wires is configured to be flush with an inner surface of a cover. A cooling system including such a semiconductor die is also provided.

A device package comprising an integrated cooling assembly comprising a semiconductor stack and a cooling channel, wherein the semiconductor stack comprises a first semiconductor device and a second semiconductor device stacked vertically above the first semiconductor device; and spacers extending between opposing surfaces of the first and second semiconductor devices to space the first semiconductor device away from the second semiconductor device, the spacers and the opposing surfaces of the first and second semiconductor devices collectively define the cooling channel therebetween; and the spacers comprise via electrically connecting the first semiconductor device and the second semiconductor device.

A semiconductor device, including a cooling body, a semiconductor unit including a wiring portion electrically connected to a semiconductor chip, and a sealing member sealing the entire semiconductor unit over a cooling surface of the cooling body. The sealing member includes a first portion and a second portion which surrounds the first portion in a plan view. The first portion seals a central portion of a main electrode of the semiconductor chip, and has a first sealing surface opposite the cooling surface of the cooling body. The second portion seals a wiring portion to thereby surround the first portion in the plan view, and has a second sealing surface opposite the cooling surface. A distance in a thickness direction of the semiconductor device from the cooling surface to the first sealing surface, is smaller than a distance in the thickness direction from the cooling surface to the second sealing surface.

A semiconductor device, including a cooling body, a semiconductor unit including a wiring portion electrically connected to a semiconductor chip, and a sealing member sealing the entire semiconductor unit over a cooling surface of the cooling body. The sealing member includes a first portion and a second portion which surrounds the first portion in a plan view. The first portion seals a central portion of a main electrode of the semiconductor chip, and has a first sealing surface opposite the cooling surface of the cooling body. The second portion seals a wiring portion to thereby surround the first portion in the plan view, and has a second sealing surface opposite the cooling surface. A distance in a thickness direction of the semiconductor device from the cooling surface to the first sealing surface, is smaller than a distance in the thickness direction from the cooling surface to the second sealing surface.

According to an embodiment a method is disclosed for designing a heat sink (500-508) comprising a container with means to guide a coolant from an inlet (100) to an outlet (200) designed to exchange heat with a component comprising the steps of generating a first mesh (600) comprising elements defining a discretized shape of a container in a massive state; generating a heat map of the container by imposing a thermal load of the component thereon thereby identifying thermal spots; repeatedly solving fluid flow equations and energy equations imposed on the first mesh through a topology optimization method by minimizing the heat sink (500-508) thermal resistance and/or maximizing the heat sink thermal uniformity; wherein the method further comprises the step of imposing a channel (400-402) on the first mesh (600) by connecting the inlet (100) with the outlet (200) via the thermal spots thereby identifying obstacles (300-302) within the first mesh (600) for the coolant; and wherein the solving step is up front performed on elements associated with the channel.

Chip packages, electronic devices and method for making the same are described herein. The chip packages and electronic devices have a heat spreader disposed over a plurality of integrated circuit (IC) devices. The heat spreader has an opening through which a protrusion from an overlaying cover extends into contact with one or more of the IC devices to provide a direct heat transfer path to the cover. Another one or more other IC devices have a heat transfer path to the cover through the heat spreader. The separate heat transfer paths allow more effective thermal management of the IC devices of the chip package.

A semiconductor module includes a heat sink configured to conduct a cooling fluid in a cooling-fluid flow direction. A first semiconductor assembly is arranged on a surface of the heat sink. The first semiconductor assembly includes a first substrate having a first dielectric material layer, and a first semiconductor element connected to the first substrate. A second semiconductor assembly is arranged on the surface of the heat sink and closest to a downstream end of the heat sink. The second semiconductor assembly includes a second substrate having a second dielectric material layer, and a second semiconductor element connected to the second substrate. The second dielectric material layer has a thermal conductivity which is higher than a thermal conductivity of the first dielectric material layer.

Many electronic devices generate significant amounts of heat during operation, especially those configured for high-performance computing often used to support machine learning/artificial intelligence (ML/AI) applications. However, operating electronic devices at increased temperatures can negatively impact their performance. While it is now common for integrated circuit packages to include a lid that can be coupled to a cooling plate providing heat dissipation, the lid is currently fabricated from copper metal which limits thermal conductivity and thus the ability to provide heat dissipation for the underlying integrated circuit. The present disclosure provide a diamond-based lid for an integrated circuit package, which can provide higher thermal conductivity than the existing copper lids.

A heat sink, a thermal module, and an electronic device are provided. The heat sink includes a base and a plurality of curved fins arranged in parallel on the base. Each curved fin has a plurality of wave peaks, with a pitch defined between any two adjacent wave peaks, and at least two of the plurality of wave peaks are different.