The present invention relates to a fluid-permeable cooler (100) for cooling a power module (208) that comprises a power substrate. The fluid-permeable cooler (101) comprises a first metal part (101), a second metal part (102) and a cooling structure (1). The first metal part (101) and the second metal part (102) are interconnected by means of a soldering process and define a cooling channel (111) which is permeable by a fluid and in which the cooling structure (1) is located.

The first metal part (101) comprises a receiving region (109) to which the power module (208) can be attached. The first metal part (101) is made from a metal material which has an expansion coefficient that is greater than the expansion coefficient of the power substrate (208). The invention also relates to a power electronics assembly (1000) having a cooler (100) of this kind and a power module (200).

A direct cooling type power module comprising, an enclosure filled with an insulating fluid, a power semiconductor device disposed inside the enclosure and a bonding unit comprising a porous layer, and a thermally conductive layer to which the power semiconductor device is bonded, and allowing the power semiconductor device to exchange heat with the insulating fluid by the porous layer and the thermally conductive layer.

A heat exchange device that is formed in a substantially rectangular shape and that cools a power semiconductor element, and a power conversion device comprising the heat exchange device, the heat exchange device including: a fin formation region in which cooling water flows in a transverse direction; and a buffer region formed in a lamination direction and facing the fin formation region, a partition wall being interposed therebetween, wherein an inlet and an outlet for the cooling water are respectively formed at at least one of both ends in a longitudinal direction, a flow path pit connecting the fin formation region and the buffer region is formed at both ends in the transverse direction, and the buffer region has a partition that divides the cooling water flowing in from the inlet and the cooling water flowing toward the outlet, and the inlet and the outlet are respectively connected to the fin formation region via the flow path pit.

A heatsink is provided for a memory and routing module with a lower and upper side, both sides having multiple semiconductor chips attached. The lower side of the module has a connection component attached for connection to a motherboard. The heatsink includes a module receiving region configured to receive a lower side of the module, including a first thermally conductive portion arranged to face the semiconductor chips, an aperture through the lower heatsink component and a thermally conductive peripheral region disposed around the module receiving region. The heatsink includes an upper heatsink component which is configured to connect to the lower heatsink component at the peripheral region to retain the module. The upper heatsink component includes a lower side. The lower side includes a second thermally conductive portion arranged to face the semiconductor chips disposed on an upper side of the module and multiple second heat dissipating elements.

A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.

A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.

A semiconductor assembly includes a semiconductor module and a unified bus. The semiconductor module a first side heatsink and a second side heatsink, a first side power device mounted to an upper surface of the first side heatsink and in electrical contact to the first side heatsink, a second side power device mounted to an upper surface of the second side heatsink and in electrical contact to the second side heatsink, and at least one cooling structure extending from a lower surface of at least one of the first side heatsink and the second side heatsink. The cooling structure is configured to provide cooling of the semiconductor module. The unified bus is communicatively connected to a capacitor assembly, the first side power device, and the second side power device. The unified bus is sintered to the first side power device and the second side power device.

An integrated circuit (IC) assembly may include a substrate and a plurality of IC die coupled to the substrate, which includes a bottom layer and a top layer coupled thereto and defining a heat exchange fluid chamber therebetween. A plurality of dielectric pillars extend within the heat exchange fluid chamber between the bottom layer and the top layer. A heat exchange fluid is within the heat exchange fluid chamber, and a wick structure within the heat exchange fluid chamber moves the heat exchange fluid in a liquid phase into the heat exchange fluid chamber. A plurality of electrically conductive through-vias extend within respective ones of the plurality of dielectric pillars and are exposed on outer surfaces of the bottom layer and the top layer. An optical waveguide layer is above the top layer.

A device includes first and second substrates. The first substrate has one or multiple first channels and one or multiple first conductors that are exposed at a first surface of the first substrate. The second substrate has one or multiple second channels and one or multiple second conductors that are exposed at a second surface of the first substrate. The first and second substrates are plasma bonded together at the first and second surfaces, forming direct electrical interconnects between the first and second conductors and direct fluidic interconnects between the first and second channels.

A device includes first and second substrates. The first substrate has one or multiple first channels and one or multiple first conductors that are exposed at a first surface of the first substrate. The second substrate has one or multiple second channels and one or multiple second conductors that are exposed at a second surface of the first substrate. The first and second substrates are plasma bonded together at the first and second surfaces, forming direct electrical interconnects between the first and second conductors and direct fluidic interconnects between the first and second channels.