An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a multi-layer patterned absorber layer on the reflective multilayer stack is provided. Disclosed embodiments include an absorber layer that includes an alloy comprising ruthenium (Ru), chromium (Cr), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), tungsten (W) or palladium (Pd), and at least one alloying element. The at least one alloying element includes ruthenium (Ru), chromium (Cr), tantalum (Ta), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), hafnium (Hf), boron (B), nitrogen (N), silicon (Si), zirconium (Zr) or vanadium (V). Other embodiments include a multi-layer patterned absorber structure with layers that include an alloy and an alloying element, where at least two of the layers of the multi-layer structure have different compositions.

A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

A method is disclosed for producing an array of parallel conductive lines in a first level of a multilevel interconnect structure of a semiconductor component. The lines are produced by direct etching (a conductive layer is produced), a hardmask line pattern is formed on the conductive layer and the line pattern is transferred to the conductive layer by etching the conductive layer relative to the hardmask lines. The hardmask lines are reduced in width prior to the pattern transfer. The width reduction is done at intended via locations. Local hardmask pillars are produced on the hardmask lines prior to the width reduction step, so that the original line width is maintained at the intended via locations. As a result, the width of the conductive lines obtained after the pattern transfer is smaller compared to conventional configurations, except in local areas corresponding to the locations of interconnect vias.

A plasma processing method includes: (a) providing a substrate to a substrate support; and (b) forming a deposited film on a surface of the substrate before etching an etching target film, and removing a part of the deposited film. (b) repeats a cycle including a first period in which a source RF signal is supplied to a chamber and a bias signal is supplied to the substrate support, a second period in which the source RF signal with a lower power level is supplied to the chamber and the bias signal with a higher power level is supplied to the substrate support, as compared to the first period, and a third period in which the source RF signal with a lower power level is supplied to the chamber and the bias signal with a higher power level is supplied to the substrate support, as compared to the second period.

The present invention provides a substrate processing method. A substrate processing method according to an embodiment may include a first step of supplying a process gas to a chamber and exciting the process gas to react with a specific film formed on the substrate to generate a reaction product, and a second step of supplying a dissociation gas to the chamber and exciting the dissociation gas to remove the reaction product from the substrate.

Provided is a composition for forming an organic film which has both embedding and planarization properties, and a method for forming an organic film and a patterning process using the composition. A composition for forming an organic film, containing: (A) an aromatic ring-containing resin; (B) a polymer containing a repeating unit containing a -diketone structure represented by the following formula (1):

##STR00001## wherein L.sub.1 is a saturated or unsaturated linear or branched divalent hydrocarbon group having 2 to 20 carbon atoms, R.sub.A and R.sub.B each are a hydrogen atom, a substituted or unsubstituted linear alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted branched or cyclic alkyl group having 3 to 20 carbon atoms, a substituted or unsubstituted aliphatic unsaturated hydrocarbon group having 2 to 20 carbon atoms and containing one or more double or triple bonds, a substituted or unsubstituted heteroalkyl group having 1 to 30 carbon atoms, a substituted or unsubstituted aryl group having 6 to 30 carbon atoms, a thiol group, a hydroxy group, an amino group, a carboxy group, or a halogen group; and (C) a solvent.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

Provided are a hard mask including an amorphous boron nitride film and a method of fabricating the hard mask, and a patterning method using the hard mask. The hard mask is provided on a substrate and used for a process of patterning the substrate, and the hard mask includes an amorphous boron nitride film.

A composition for forming an organic film containing (A) a resin or compound for forming an organic film, (B) a compound represented by the general formula (1), and (C) a solvent,

##STR00001## wherein R.sub.1 is a terminal group represented by the general formula (2), X is an n1-valent organic group having 2 to 50 carbon atoms, and n1 represents an integer of 2 to 8,

##STR00002## wherein R.sub.2 is a monovalent organic group, wherein the monovalent organic group contains at least any of structures having fluorine atoms represented by the general formula (3), m1 is 1 or 2, wherein when m1 is 1, Z represents a single bond or a divalent organic group optionally containing a heteroatom, and when m1 is 2, Z represents a trivalent organic group optionally containing a heteroatom,

##STR00003##