A method of fabricating a semiconductor device includes forming a first shallow trench isolation structure in a first region of a substrate and second shallow trench isolation structures in a second region of the substrate. The method also includes forming a mask layer over the substrate, the first shallow trench isolation structure, and the second shallow trench isolation structures. The method further includes etching the mask layer and second shallow trench isolation structures in the second region sequentially to form a semiconductor protrusion between the second shallow trench isolation structures.

A method of forming high quality a-BN layers. The method includes use of a precursor chemistry that is particularly suited for use in a cyclical deposition process such as in chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In brief, new methods are described of forming boron nitride (BN) layers from precursors capable of growing amorphous BN (a-BN) films by CVD, ALD, or the like. In some cases, the precursor is or includes a borane adduct of hydrazine or a hydrazine derivative.

Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional materials may include a patterned photoresist material. The methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. The methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. The methods may include etching the silicon-containing material with a fluorine-containing precursor. The metal dopant may enhance an etch rate of the silicon-containing material. The methods may include removing the metal-doped boron-containing material from the substrate with a halogen-containing precursor.

Embodiments herein are directed to localized wafer thickness correction. In some embodiments, a method may include providing a substrate including an upper surface having a raised portion extending above a plane defined by the upper surface, and a non-raised portion adjacent the raised portion. The method may further include performing a metrology scan of the upper surface to determine a first dimension of the raised portion and a second dimension of the non-raised portion, and depositing a hardmask over the upper surface, including over the raised portion and the non-raised portion. The method may further include directing ions to the hardmask, wherein a first dose of the ions over the raised portion is greater than a second dose of the ions over the non-raised portion, and performing a first etch to the hardmask to remove the hardmask over the raised portion, wherein the hardmask remains over the non-raised portion.

A semiconductor device includes a substrate. The semiconductor device further includes a conductive structure in the substrate. The semiconductor device further includes an etch stop layer over the substrate. The semiconductor device further includes an interlayer dielectric (ILD) over the etch stop layer. The semiconductor device further includes a dual damascene conductive element in the ILD, wherein the dual damascene conductive element extends through the etch stop layer to electrically connect to the conductive structure, and the dual damascene conductive element has a line end roughness (LER) ranging from 3.3 nanometers (nm) to 5.3 nm.

A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

A method of patterning a substrate includes exposing a photoresist layer on the substrate with a pattern of actinic radiation to form a chemically reactive surface pattern, and coating, at the track system, a spin-on-material to convert the chemically reactive surface pattern to a photoresist surface mask pattern. The method further includes etching the photoresist layer using the photoresist surface mask pattern as a first etch mask to form a photoresist mask pattern, and etching a layer to be etched with the photoresist mask pattern as a second etch mask.

Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., features having an aspect ratio 30:1) within stacked structures to reduce or eliminate problems that occur during conventional HAR etch processes. More specifically, novel hard mask layers and methods are provided to improve the etch profile, post-etch surface roughness and CD uniformity of high aspect ratio features etched within hard mask layers, as well as the etch selectivity to layer(s) underlying the hard mask layers or other semiconductor materials exposed on the substrate surface.

A semiconductor device includes a substrate, a channel region, a source/drain feature, a gate structure, a dielectric structure, a first crystalline hard mask layer, and a first amorphous hard mask layer. The channel region is disposed over a substrate. The isolation feature is disposed over the substrate and alongside the channel region. The source/drain feature interfaces a sidewall of the channel region, wherein the source/drain feature and the channel region are disposed along a first direction, and along a second direction different from the first direction. The gate structure is disposed over the channel region. The dielectric structure is disposed over the isolation feature and interfaces the source/drain feature. The first crystalline hard mask layer is disposed over the dielectric structure. The first amorphous hard mask layer is disposed in the first crystalline hard mask layer.