An electrical connection structure includes a dielectric layer stack of a plurality of dielectric layers including a first dielectric layer as an uppermost layer, and a second dielectric layer under the first dielectric layer, a plurality of metal layers in the plurality of dielectric layers, a via stack in the plurality of dielectric layers that connects the plurality of metal layers, an upper metal layer on the dielectric layer stack over the via stack, and an upper dielectric layer on the dielectric layer stack and including an upper dielectric layer opening over the upper metal layer and the via stack. A number of first vias in the first dielectric layer, may be less than or equal to a number of second vias in the second dielectric layer, and the number of second vias in the second dielectric layer may be less than or equal to 3.

Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.

Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the sealed cavities.

A semiconductor device including a semiconductor substrate, an interlayer insulation layer on the semiconductor substrate, a first via structure passing through the semiconductor substrate and the interlayer insulation layer and having a first diameter, and a second via structure passing through the semiconductor substrate and the interlayer insulation layer, the second via structure having a second diameter greater than the first diameter, at a same vertical level may be provided. A sidewall of the first via structure may include at least one undercut region horizontally protruding toward a center of the first via structure, and an outer sidewall of the second via structure may be in contact with either the semiconductor substrate or the interlayer insulation layer at an area above the undercut region.

The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.

A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: forming a sacrificial layer in a concave in a metal layer; recessing the sacrificial layer; filling a metal-organic framework layer in the concave; and removing the sacrificial layer to form an air gap in the concave.

A manufacturing method of a semiconductor structure includes the following steps. A silicon substrate is provided, and a patterning process is performed to the silicon substrate for forming first trenches in the silicon substrate. A part of the silicon substrate is patterned to be a first fin-shaped structure located between two of the first trenches adjacent to each other in a horizontal direction by the patterning process, and a top corner of the first fin-shaped structure protrudes outwards in the horizontal direction. An oxidation process is performed to the first fin-shaped structure, and a part of the first fin-shaped structure is oxidized to be an oxide layer by the oxidation process. A removing process is performed for removing the oxide layer, and the top corner of the first fin-shaped structure becomes a curved sidewall via the oxidation process and the removing process.

An exemplary method according to the present disclosure includes forming a first dielectric layer over a first conductive feature, forming a second dielectric layer over the first dielectric layer, forming a patterned mask over the second dielectric layer, performing a first etching process to form a trench extending through the first dielectric layer and the second dielectric layer to expose a top surface of the first conductive feature, where etchant of the first etching process modifies a portion of the first dielectric layer exposed by the trench, performing a second etching process to remove the patterned mask and the modified portion of the first dielectric layer, where etchant of the second etching process further reacts with a part of a remaining portion of the first dielectric layer to cause a volume expansion of the remaining portion of the first dielectric layer, and forming a second conductive feature in the trench.