A pick-up structure for a memory device and method for manufacturing memory device are provided. The pick-up structure includes a substrate and a plurality of pick-up electrode strips. The substrate has a memory cell region and a peripheral pick-up region adjacent thereto. The pick-up electrode strips are parallel to a first direction and arranged on the substrate in a second direction. The second direction is different from the first direction. Each pick-up electrode strip includes a main part in the peripheral pick-up region and an extension part extending from the main part to the memory cell region. The main part is defined by fork-shaped patterns of a first mask layer. The extension part has a width less than that of the main part, and the extension part has a side wall surface aligned with a side wall surface of the main part.

According to some example embodiments, an integrated circuit includes a first inter-wiring insulating film on a substrate, a first and second wiring patterns spaced apart from each other on the first inter-wiring insulating film, a first etch stop layer on the first inter-wiring insulating film, the first and second wiring patterns, and a second inter-wiring insulating film on the first etch stop layer. Each of the first and second wiring patterns includes a first lower pattern in the first inter-wiring insulating film, and a first upper pattern on an upper surface of the first inter-wiring insulating film. The first etch stop layer extends along profiles of the upper surface of the first inter-wiring insulating film, and a side face and an upper surface of the first upper pattern. The second inter-wiring insulating film defines a first void between the first wiring pattern and the second wiring pattern.

A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

The present invention provides a method for forming self-transformed support plates in shallow trench isolation for advanced semiconductor devices, in which after a photolithography process to define active areas on a silicon substrate, an additional photomask is implemented to add a support plate patterning layer in areas where silicon will be etched during a STI etching step to form STI trenches. Tiny silicon support plates inside the STI trenches are formed after the silicon etching. These silicon support plates may provide mechanical support to hold neighboring patterned strips where the active areas are defined or neighboring active areas islands, and preventing them from bending, deformed or shifting. An alignment of photomask pattern at following photolithography process is eased.

A semiconductor device includes a semiconductor layer including a trench, wherein the trench is adjacent a mesa, a first metal silicide layer on a top portion of the mesa, and a second metal silicide layer on a bottom portion of the trench. The first metal silicide layer has a thickness that is no more than about 1 to 1.5 times greater than a thickness of the second metal silicide layer. Related methods of forming a semiconductor device are disclosed.

A manufacturing method of a semiconductor structure includes forming a first interconnect structure over a first semiconductor substrate; forming a through substrate via (TSV) to penetrate through the first semiconductor substrate and extend into the first interconnect structure, where the TSV includes a first surface in the first interconnect structure and a second surface opposite to the first surface; and forming a first bonding conductor on the first interconnect structure to be electrically coupled to the TSV through the first interconnect structure, where the first bonding conductor includes a first bonding surface facing away the first interconnect structure, and a boundary of the first bonding surface of the first bonding conductor overlaps a boundary of the first surface of the TSV.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

A method for manufacturing an interconnect structure includes: forming first and second etch stop layers respectively on first and second lower conductive portions, the first and second etch stop layers having different configurations; forming a dielectric layer to cover the first and second etch stop layers; performing a first etching process to form a first hole and a second hole in the dielectric layer to expose at least one of the first and second etch stop layers; performing a second etching process to form a first opening extending downwardly from the first hole and through the first etch stop layer, and to form a second opening extending downwardly from the second hole and through the second etch stop layer; and forming a first upper conductive portion in the first hole and the first opening, and forming a second upper conductive portion in the second hole and the second opening.

A device includes semiconductor channel region, source/drain regions, a source/drain contact, a first dielectric layer, a second dielectric layer, and a tungsten via. The source/drain regions are at opposite sides of the semiconductor channel region. The source/drain contact is over one of the source/drain regions. The first dielectric layer is over the source/drain contact. The second dielectric layer is over the first dielectric layer. The tungsten via extends through the first and second dielectric layers to the source/drain contact. The tungsten via includes a first portion over the source/drain contact and a second portion over the first portion. The second portion includes a tungsten sidewall laterally offset from a tungsten sidewall of the first portion, and a tungsten surface interfacing a top surface of the first dielectric layer.