A wafer processing method includes forming a start point of division along division lines, providing, on a front surface of the wafer, a protective member for protecting the front surface of the wafer, grinding a back surface of the wafer to a desired thickness, forming division grooves in the division lines to divide the wafer into individual device chips, providing an expandable sheet to the back surface of the wafer and removing the protective member from the front surface of the wafer, coating the front surface of the wafer with an adhesive liquid having flowability, expanding and shrinking the sheet so as to allow the adhesive liquid to enter each of the division grooves and to discharge the adhesive liquid from the division grooves, and removing the adhesive liquid from the front surface of the wafer to clean a side surface of each of the division grooves.

A chip manufacturing method includes: preparing a wafer unit having a protective member fixed to one surface of a wafer and having a recess and a loop-shaped protrusion surrounding the recess on the other surface side of the wafer, the protective member including a first sheet in contact with the wafer, a resin layer stacked on the first sheet, and a second sheet stacked on the resin layer; processing the wafer and the protective member along a boundary between the recess and the loop-shaped protrusion to separate the recess and the loop-shaped protrusion from each other; and after separating of the recess and the loop-shaped protrusion, holding the protective member side of the wafer on a holding table and dividing the wafer from the other surface side to manufacture a plurality of chips.

A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip via a second bonding material. The first semiconductor chip includes: a protective film; and a first pad electrode exposed from the protective film in a first opening portion of the protective film. The second semiconductor chip is mounted on the first pad electrode of the first semiconductor chip via the second bonding material. The second bonding material includes: a first member being in contact with the first pad electrode; and a second member interposed between the first member and the second semiconductor chip. The first member is a conductive bonding material of a film shape, and the second member is an insulating bonding material of a film shape.

Provided is a method of manufacturing a semiconductor package, the method including: forming a bonding layer on a carrier, forming a redistribution substrate on the bonding layer, mounting a plurality of semiconductor chips on the redistribution substrate, forming a package structure for a plurality of semiconductor packages; bonding an ultraviolet (UV)-curable adhesive sheet to a surface of the package structure opposite the bonding layer and redistribution substrate; separating or removing the carrier and the bonding layer from the package structure; forming an under bump metallurgy (UBM) layer and forming an external connection conductor on the redistribution substrate; cutting the package structure into the plurality of semiconductor packages; irradiating the UV-curable adhesive sheet with UV rays, after cutting the plurality of semiconductor packages; and separating the plurality of semiconductor packages from the UV-curable adhesive sheet.

A dicing method including the steps of: bonding a first wafer having a first wafer resistivity and a second wafer having a second wafer resistivity higher than the wafer first resistivity, thereby forming a bonded wafer; irradiating the bonded wafer with a laser while varying focal lengths in a thickness direction of the bonded wafer, thereby forming a plurality of modified regions along a dicing line; and dicing the bonded wafer along the dicing line by performing an expansion process on the bonded wafer formed with the modified regions.

A manufacturing method for a semiconductor device includes a preparation step of preparing a wafer that has a first surface on one side and a second surface on the other side, a first supporting step of supporting the wafer from the first surface side by a first member of a plate shape, a thinning step of thinning the wafer in a state where the wafer is supported by the first member, a second supporting step of supporting the wafer from a peripheral edge portion side of the second surface by a second member of a plate shape that exposes an inner portion of the second surface after the thinning step, and a removing step of removing the first member from the first surface side in a state where the wafer is supported by the second member.

Methods, systems, and devices for manufacturing technique for mechanical debonding of a carrier wafer from other structures in a stacked semiconductor system are described. The carrier wafer may include a first bonding layer that includes a first plurality of cavities. The stacked semiconductor system may also include a device wafer with a second bonding layer that is fusion bonded with the first bonding layer of the carrier wafer. The second bonding layer of the device wafer may include a second plurality of cavities.

A method of manufacturing a laminated wafer with a processed outer circumference includes acquiring a value of joint misalignment between a first wafer and a second wafer of the laminated wafer by measuring the positions of outer circumferences of the first and second wafers, holding the second wafer of the laminated wafer on a holding surface of a holding mechanism, acquiring the position of the first wafer with respect to the holding mechanism while the laminated wafer is being held by the holding mechanism, acquiring the position of the second wafer with respect to the holding mechanism on the basis of the acquired value of joint misalignment and the acquired position of the first wafer, and processing the outer circumference of the first wafer on the basis of the acquired position of the second wafer as a reference.

Bonded die structures and methods of fabricating bonded die structures with improved stress distribution. A bonded die structure may include a second die bonded to a first die. The sizes, shapes and/or relative position of the first die with respect to the second die may be configured to minimize stress concentrations in the bonded die structure. In some embodiments, a length dimension of a corner region of the second die may be less than a length dimension of the adjacent corner region of the first die, which may aid in redistributing stress away from the corner of the first die. An offset distance between the corner of the second die and the corner of the first die may also be controlled to minimize stress applied to the corner of the first die along a vertical direction. Accordingly, crack formation may be reduced, and device performance and yields may be improved.

A temporary adhesive without the formation of voids between a support and a wafer. A temporary adhesive for separatably attaching a support to a circuit side of a wafer to process a rear surface of the wafer, the temporary adhesive including a component (A) that is cured by a hydrosilylation reaction; a polymerization inhibitor (B) having a 5% mass decrease temperature of 80 C. or higher as measured using a Tg-DTA; and a solvent (C). The component (A) may include a polysiloxane (A1) including a polyorganosiloxane (a1) containing a C.sub.1-10 alkyl group and a C.sub.2-10 alkenyl group, and a polyorganosiloxane (a2) containing a C.sub.1-10 alkyl group and a hydrogen atom; and a platinum group metal-based catalyst (A2). The polymerization inhibitor (B) may be a compound of formula (1): ##STR00001##
(wherein R.sup.7 and R.sup.8 are each a C.sub.6-40 aryl group, or a combination of a C.sub.1-10 alkyl group and a C.sub.6-40 aryl group).