A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

A package structure includes a first dielectric layer disposed on a first patterned circuit layer, a first conductive via in the first dielectric layer and electrically connected to the first patterned circuit layer, a circuit layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and covering the circuit layer, a second patterned circuit layer on the second dielectric layer and including conductive features, a chip on the conductive features, and a molding layer disposed on the second dielectric layer and encapsulating the chip. The circuit layer includes a plurality of portions separated from each other and including a first portion and a second portion. The number of pads corresponding to the first portion is different from that of pads corresponding to the second portion. An orthographic projection of each portion overlaps orthographic projections of at least two of the conductive features.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

A cutting apparatus for dividing a wafer that is stuck to an adhesive tape in which the adhesive layer is cured by ultraviolet light and that is supported by an annular frame through the adhesive tape, into individual chips, includes: a holding unit having a frame support section that supports the annular frame, and a wafer table that is formed of a transparent body and supports the wafer; a cutting unit including, in a rotatable manner, a cutting blade for cutting the wafer; and an ultraviolet light applying unit that applies ultraviolet light, the ultraviolet light applying unit being disposed facing the cutting blade in such a manner that the wafer table is interposed therebetween. The ultraviolet light applying unit applies ultraviolet light to a region where the wafer is to be cut by the cutting blade, to form a cured region where the adhesive layer is cured.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.

As an example of a semiconductor device is disclosed. The semiconductor device 1 includes a semiconductor die 3 and a wiring layer 5a to which the semiconductor die 3 is attached. The semiconductor die 3 includes a semiconductor substrate 3a having a first surface and a second surface opposite thereto, a plurality of terminal electrodes 3b provided on the first surface of the semiconductor substrate 3a, and a cured resin layer 3c. The cured resin layer 3c is provided on the first surface of the semiconductor substrate 3a so as to cover the plurality of terminal electrodes 3c. The semiconductor die 3 can be, for example, a bride die that connects a semiconductor die 2a and a semiconductor die 2b to each other.

A semiconductor substrate including a front side and a backside and including a good die region having a plurality of semiconductor chips, a dummy die region having a plurality of dummy chips in an arc shape along an outer portion of the good die region, a plurality of first bump pads at a first interval on the backside of each of the plurality of semiconductor chips, and a plurality of second bump pads at a second interval on the backside of at least one of the plurality of dummy chips. The second interval is smaller than the first interval. The plurality of first bump pads are in a first matrix arrangement and the plurality of second bump pads are alternately arranged in a second matrix arrangement, the second matrix arrangement including both the first matrix arrangement and the first matrix arrangement shifted by a desired distance in a horizontal direction.

A semiconductor device manufacturing method of manufacturing a semiconductor device by machining a substrate including a first surface and a second surface opposite to the first surface is provided. The semiconductor device manufacturing method including: forming a first trimmed part by performing trimming of the substrate from the first surface side; forming a second trimmed part by performing trimming of the substrate from the first surface side; forming an adhesive layer on the first surface using a spin coating method including rotating the substrate around a rotation axis; fixing the substrate to a support member via the adhesive layer; and grinding the substrate from the second surface side to decrease a dimension in a thickness direction of the substrate. The second trimmed part includes a part which is located on an inner side with respect to the first trimmed part in a radial direction from the rotation axis.

A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.