A method is of manufacturing a plurality of devices by dividing a device wafer along a plurality of planned dividing lines intersecting each other, the device wafer having a device surface on which each of the devices is formed in each of regions partitioned by the planned dividing lines. The method includes: directly bonding a carrier plate to the device surface of the device wafer; after the bonding of the carrier plate, dicing the device wafer supported by the carrier plate along the planned dividing lines to thereby form a plurality of devices; and after the forming of the plurality of devices, separating the plurality of devices from the carrier plate.

According to one embodiment, a manufacturing method of a semiconductor device, comprising: attaching a dicing tape to a ring frame, the dicing tape including a base, an adhesive provided on an upper surface of the base and including a material capable of changing in property by light irradiation, and a releasing film; executing light irradiation from below the base, thereby making an adhesivity of a first portion overlapping the releasing film, in an upper surface of the adhesive, different from an adhesivity of a second portion not overlapping the first portion, in the upper surface of the adhesive; attaching a work piece to the adhesive; and singulating a plurality of semiconductor devices by dicing the work piece.

Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

A semiconductor wafer is diced along a plurality of dicing lines in a first direction and a second direction different from the first direction so that a chip is cut out from an effective area. The semiconductor water includes a film formation pattern. At least one dicing line included in the plurality of dicing lines is an on-pattern dicing line which overlaps the film formation pattern in its entire or partial length.

A wafer thinning tape and a preparation method thereof, and a wafer grinding method are provided. The wafer thinning tape includes a tape layer, a base film layer, and a conductive coating that are successively stacked, where the base film layer and the conductive coating constitute an antistatic base film; the raw materials of the tape layer include acrylic adhesive, curing agent, and antistatic agent, and the mass dosage of curing agent is 3%-4% that of the acrylic adhesive, and the mass dosage of antistatic agent is 1%-2% that of the acrylic adhesive; the base film layer is TPU film; the conductive coating is silver nanowire coating. The wafer thinning tape can be applied to wafer grinding, has excellent antistatic property, and can effectively inhibit the peeling static electricity; at the same time, it also has the advantages of peeling without residue and preventing water penetration.

A method includes preparing a protective film including a base film and a protective layer laminated on a surface of the base film, mounting the protective film on a semiconductor wafer having a rear surface attached to a dicing tape and a front surface positioned opposite to the rear surface, the protective layer being disposed on the front surface, irradiating the rear surface of the semiconductor wafer with a dicing laser, removing the base film of the protective film from the semiconductor wafer, dividing the semiconductor wafer into individual semiconductor chips, and removing the protective layer from the individual semiconductor chips.

A die bonding apparatus includes a push-up unit, a head having a collet that sucks a die, and a control device. The control device is configured to suck a dicing tape using a dome plate; land the collet onto the die using the head; suck the die using the collet; lift plural blocks from the dome plate; stop the outermost block disposed on the outermost side among the plural blocks from lifting at a height where the die is peeled off from the dicing tape; and lift blocks other than the outermost block among the plural blocks higher than the outermost block to a predefined height.

A device wafer processing method includes a protective film coating step of coating a face side of a device wafer with a protective film, a laser processing step of applying a laser beam having a wavelength absorbable by the device wafer to the device wafer along streets and forming laser processing grooves that divide a device layer, a tape affixing step of affixing a tape to the protective film on the device wafer, a holding step of holding the face side of the device wafer by a holding table via the tape and exposing a reverse side of the device wafer, and a cutting step of cutting the device wafer held on the holding table, by a cutting blade from the reverse side along the streets, and dividing the device wafer into individual devices.

A method for manufacturing a semiconductor device includes preparing a temporary fixing structure body in which semiconductor elements each including a first surface on which a connection terminal is formed and a second surface are attached to a temporary fixing material, forming a curable bonding adhesive layer on the second surface of each of the semiconductor elements, attaching a carrier to one surface of the curable bonding adhesive layer opposite to the semiconductor elements, fixing the semiconductor elements to the carrier by curing the curable bonding adhesive layer, and removing the temporary fixing material. The semiconductor elements are attached onto the temporary fixing material such that the first surface of each of the semiconductor elements is directed toward the temporary fixing material, and are encapsulated with an encapsulant material such that the second surface of each of the semiconductor elements is exposed from an encapsulant material layer.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 2633 mm, using pick-and-place assembly.