The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

A method of manufacturing a semiconductor package includes: hybrid-bonding a semiconductor chip, including a through-silicon via, to an upper surface of a semiconductor wafer, wet-etching a surface of the semiconductor chip to expose the through-silicon via, covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer, removing an upper surface of the encapsulation layer to expose the through-silicon via, and forming a redistribution structure electrically connected to the through-silicon via.

A semiconductor device includes a substrate, a first cell having a first functionality, and a second cell having a second functionality. The first cell includes a first portion on a first side of the substrate, wherein the first portion includes a first conductive element; a second portion on a second side of the substrate, wherein the second portion includes a second conductive element; and a first conductive via extending through the substrate and electrically connecting the first conductive element to the second conductive element. The second cell includes a third portion on the first side of the substrate, wherein the third portion includes a third conductive element; a fourth portion on the second side of the substrate, wherein the fourth portion includes a fourth conductive element; and a second conductive via extending through the substrate and electrically connecting the third conductive element to the fourth conductive element.

The present disclosure relates to a method, which includes forming a patterned mask layer having an opening disposed on a first surface of a substrate; performing a cyclic etching and deposition processes from the first surface to form a recess corresponding to the opening and a liner layer disposed thereon; performing a first removal process to remove the liner layer for exposing a portion of the substrate in the recess; and performing a trimming process to remove the portion of the substrate in the recess.

Disclosed is a semiconductor structure including a substrate, a capacitor structure, an interlayer dielectric, a contact, a protective layer, and a conductive hole. The capacitor structure is disposed in the substrate. The interlayer dielectric is disposed on the substrate, and exposes a portion of the capacitor structure. The contact is disposed in the interlayer dielectric, and is electrically connected to the capacitor structure. The protective layer is disposed on the interlayer dielectric, and covers the contact. The conductive hole penetrates the protective layer and the interlayer dielectric. A top surface of the conductive hole is higher than a top surface of the contact. A manufacturing method of a semiconductor structure is also provided.

Landing metal layers with improved adhesion to semiconductor substrates are described, along with semiconductor structures including the landing metal layers and components using the landing metal layers. An example semiconductor device includes a substrate with top and bottom surfaces, a landing metal layer over the top surface of the substrate, a via that extends through the substrate, and a bottom side metal layer. The bottom side metal layer extends over sidewalls of the via and electrically contacts an underside of the landing metal layer. For improved adhesion, the landing metal layer is diffused at least in part into the top surface of the substrate. The landing metal layer is diffused into the top surface of the substrate by an annealing or alloying process, and the techniques described herein help to avoid the delamination of the landing metal layer from the top surface of the substrate.

A manufacturing method of a semiconductor device includes forming a semiconductor layer of a first conductivity type that is located on a substrate, simultaneously forming a first trench having the semiconductor layer as a bottom surface and a second trench that runs through the semiconductor layer, simultaneously forming an insulator that fills up the first trench and an insulating layer that covers the second trench, removing a part of the insulator such that the bottom surface of the first trench is not exposed, removing a part of the insulating layer such that the semiconductor substrate is exposed in the second trench, embedding in the first trench a first conductor that is separated from the semiconductor layer, and embedding in the second trench a second conductor that is in contact with the semiconductor substrate. A width of the second trench is greater than a width of the first trench.

Methods, systems, and devices for power and signal distribution in stacked semiconductor systems are described. A semiconductor system may include a distribution component configured to communicate power, signals, or both with a logic component and memory component(s) of the semiconductor system. The distribution component may include power delivery circuitry to provide separate power to the memory component(s) and the logic component, data serialization/deserialization circuitry to communicate data signals with the logic component, or both. The distribution component may convey power, data signals, or both to the logic component using conductive vias that pass through the memory components and bypass interface circuitry of the memory component(s). The distribution component may include clock circuitry that receives, generates, or both, one or more clock signals and provides the one or more clock signals for I/O functionality of the distribution component, the logic component, the interface circuitry, or any combination thereof.

A semiconductor device including a semiconductor substrate, an interlayer insulation layer on the semiconductor substrate, a first via structure passing through the semiconductor substrate and the interlayer insulation layer and having a first diameter, and a second via structure passing through the semiconductor substrate and the interlayer insulation layer, the second via structure having a second diameter greater than the first diameter, at a same vertical level may be provided. A sidewall of the first via structure may include at least one undercut region horizontally protruding toward a center of the first via structure, and an outer sidewall of the second via structure may be in contact with either the semiconductor substrate or the interlayer insulation layer at an area above the undercut region.

Semiconductor devices having nano through substrate vias (TSVs), and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a semiconductor substrate that has a first surface and a second surface opposite the first surface. A trench is formed in the first surface and filled with a dielectric material and a TSV extends from the first surface to the second surface within the footprint of the trench. In some embodiments, the TSV includes a conductive material that includes a first portion and a second portion. The first portion includes a first end at the first surface and a second end with a larger cross-sectional area than the first end. Similarly, the second portion includes a third end coupled to the second end and a fourth end at the second surface with a larger cross-sectional area than the third end.