A composition for semiconductor processing includes abrasive particles, and a dishing control additive, comprising a first dishing control additive and a second dishing control additive. The first dishing control additive includes a compound having a betaine group and a salicylic group or a derivative thereof, and the second dishing control additive includes an azole-based compound. The first dishing control additive includes 0.07 parts by weight or more based on 100 parts by weight of the abrasive particles, and the second dishing control additive includes 0.13 parts by weight or less based on 100 parts by weight of the abrasive particles.

A semiconductor device includes a substrate having a first and second surface opposite to each other, and an active region on the first surface and defined by a first isolation region; a plurality of active fins on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

A method of manufacturing a semiconductor device may include bonding a carrier substrate onto a device wafer using an adhesive member, wherein the adhesive member includes a base film, a device adhesive film disposed on a lower surface of the base film and contacting the device wafer, and a carrier adhesive film disposed on an upper surface of the base film and contacting the carrier substrate. The device adhesive film includes a gas blowing agent, and the carrier adhesive film may not include a gas blowing agent.

The semiconductor stacked package including a semiconductor die. The semiconductor die includes a substrate, a transistor, and a through-silicon-via (TSV) structure. The transistor is over the substrate. The TSV structure penetrates the substrate and comprises a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is between the first conductive layer and the second conductive layer. The method of manufacturing the same includes the following steps: forming a via hole in a substrate; forming a first conductive layer in the via hole; forming a dielectric layer in the via hole and over the first conductive layer; forming a second conductive layer in the via hole and over the dielectric layer; and forming a transistor over the substrate. The first conductive layer, the dielectric layer, and the second conductive layer collectively form a through-silicon-via (TSV) structure.

A chip includes a chip substrate having a first thickness and including a back surface. The back surface includes an etched portion with an etching depth that is less than the first thickness. The chip further includes a first thin film including a dielectric material and located on the back surface. The chip further includes a second thin film including a barrier layer material and located on the first thin film. The chip further includes a third thin film including a metal material, embedded in the chip substrate, and located on the second thin film. The chip further includes a coverage layer including nitride or carbon nitride and located on the first thin film, the second thin film, and the third thin film.

A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

A package structure according to the present disclosure includes a bottom substrate, a bottom interconnect structure over the bottom substrate, a top interconnect structure disposed over the bottom interconnect structure and including a metal feature, a top substrate over the top interconnect structure, and a protective film disposed on the top substrate. The protective film includes an interfacial layer on the top substrate, at least one dipole-inducing layer on the interfacial layer, a moisture block layer on the at least one dipole-inducing layer, and a silicon oxide layer over the moisture block layer. The at least one dipole-inducing layer includes aluminum oxide, titanium oxide or zirconium oxide.

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

A semiconductor device with a two-sided redistribution layer is disclosed. The semiconductor device comprises a host device and one or more memory stack cubes. A redistribution layer is disposed between and couples the host device and the memory stack cubes. This redistribution layer features an edge surface extending between the host device and the memory stack cubes. The semiconductor device includes first connective circuitry that extends through the redistribution layer, is coupled with the host device, and is exposed at the edge surface of the redistribution layer. Additionally, second connective circuitry extends through the redistribution layer, is coupled with the memory stack cubes, and is exposed at the edge surface of the redistribution layer. Connective structures couple the first and second connective circuitry exposed at the edge surface of the redistribution layer.

An apparatus includes a through-silicon via (TSV) including a conductive material; a first contact plug having an upper surface and a bottom surface directly connected to an upper surface of the TSV; a first wiring directly connected to the upper surface of the first contact plug; a second wiring having an upper surface; a second contact plug having an upper surface and a bottom surface directly connected to the upper surface of the second wiring; and a third wiring directly connected to the upper surface of the second contact plug; wherein the first wiring and the third wiring are in a substantially same level.