There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device may include a first interlayer insulating film containing therein a plurality of pores, a first line structure in the first interlayer insulating film, an inserted insulating film extending along and on a upper surface of the first interlayer insulating film and in contact with the first interlayer insulating film, a barrier insulating film in contact with the inserted insulating film and extending along an upper surface of the inserted insulating film and an upper surface of the first line structure, a second interlayer insulating film on the barrier insulating film and a second line structure disposed in the second interlayer insulating film and connected to the first line structure.

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Provided are an interconnector and an electronic apparatus including the interconnector. The interconnector includes: a metal layer; a dielectric layer surrounding at least a portion of the metal layer; and an interlayer disposed between the metal layer and the dielectric layer and including a ternary metal oxide.

An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.

Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

An electronic system includes a first device and a second device bonded to the first device. The first device includes: a semiconductor substrate with an opening; a stack having metal layers and conductive vias; and a conductive layer including aluminum having a first face in contact with the stack and a second face, opposite the first face, that is partially exposed through the opening. The metal layers and the conductive vias of the stack are made of a conductive material different from aluminum.

A chip structure having an interconnect and a manufacturing method thereof include a buffer layer formed between an upper metal structure and a passivation layer under the upper metal structure so as to prevent fractures, such as cracks, from occurring in the passivation layer due to difference of stress between the upper metal structure and the passivation layer.

Provided herein is a high temperature metallization structure with a refractory diffusion barrier for high-speed computing, RF, High Temperature Controls, and mmWave electronics and components.