The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over first and second fin structures, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a first source/drain (S/D) epitaxial structure formed adjacent to the gate structure in the first fin structure. The S/D epitaxial structure comprises first and second S/D epitaxial layers. The semiconductor structure may include a second S/D epitaxial structure formed adjacent to the gate structure in the second fin structure. A contact structure may be formed over the first and second S/D epitaxial structures.

A method of fabricating a pixel array substrate includes forming a semiconductor layer on a substrate, forming a metal layer stack on the semiconductor layer, forming a photoresist pattern on the metal layer stack, and removing part of the metal layer stack and the semiconductor layer not covered by the photoresist pattern at one time using a dry etching process to form a source, a drain, and a semiconductor pattern of an active device. The metal layer stack includes a first titanium layer, an aluminum layer, and a second titanium layer. The semiconductor pattern has a groove located between the source and the drain. The source and the drain respectively have a source edge and a drain edge opposite to each other, which defines two opposite side walls of the groove respectively. A pixel array substrate produced by using the method of fabricating the pixel array substrate is also disclosed.

Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber.

The invention is to provide a semiconductor manufacturing apparatus system and a semiconductor device manufacturing method for reducing particles having an adverse effect in a manufacturing step of a semiconductor device. A semiconductor device manufacturing system, includes: a semiconductor manufacturing apparatus; and a platform connected to the semiconductor manufacturing apparatus via a network and in which a particle reduction processing is executed, in which the particle reduction processing includes: a step of acquiring a particle characteristic value by using a sample processed by the semiconductor manufacturing apparatus; a step of specifying a component of the semiconductor manufacturing apparatus leading to a particle generation based on the acquired particle characteristic value and correlation data by machine learning; a step of defining a cleaning condition for cleaning the semiconductor manufacturing apparatus based on the specified component; and a step of cleaning the semiconductor manufacturing apparatus using the defined cleaning condition, and the correlation data is correlation data between the particle characteristic value acquired in advance and the component.

An etching method includes forming a recess overlapping an opening of a mask by etching a silicon layer, forming a protective layer on at least a side wall of the recess, and etching a bottom of the recess, in which the forming of the protective layer includes forming a precursor layer on at least the side wall of the recess, and modifying the precursor layer into the protective layer, the etching of the bottom of the recess includes supplying a pulse of source radio frequency power from a radio frequency power supply, and supplying a pulse of bias power to a support configured to support the substrate from a bias power supply, and a period during which the forming of the precursor layer is performed does not overlap a period during which the modifying of the precursor layer is performed.

A method of plasma processing includes generating plasma by coupling a source power pulse to a plasma processing chamber containing a substrate holder configured to support a substrate. The plasma includes first ions having a first mass and second ions having a second mass greater than the first mass. The ion density ratio of the second ions to the first ions is a first ratio. The method further includes delivering an energetic ion flux of second ions to the substrate by applying a delayed bias power pulse to the substrate holder after a delay between the source power pulse and the delayed bias power pulse. The delay is chosen based on the diffusion time constants of the first ions and the second ions so that the ion density ratio of the second ions to the first ions is a second ratio that is greater than the first ratio.

Provided is an etching method. The etching method includes loading a substrate into a process chamber, wherein the process chamber includes a first chamber part and a second chamber part, and the substrate is loaded into the second chamber part, supplying high-density gas plasma to the first chamber part, supplying ultra-low electron temperature plasma to the second chamber part using at least a portion of the high-density gas plasma, adsorbing radicals of the ultra-low electron temperature plasma to a surface of the substrate, and applying a bias to the substrate to accelerate at least one of ions or electrons of the ultra-low electron temperature plasma so as to collide with the substrate.

Embodiments provided herein include an apparatus and methods for the plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to reducing defectivity in features formed on the surface of the substrate, improving plasma etch rate, and increasing selectivity of etching material to mask and/or etching material to stop layer. In some embodiments, the apparatus and methods enable processes that can be used to prevent or reduce the effect of trapped charges, disposed within features formed on a substrate, on the etch rate and defect formation. In some embodiments, the plasma processing methods include the synchronization of the delivery of pulsed-voltage (PV) waveforms, and alternately the delivery of a PV waveform and a radio frequency (RF) waveform, so as to allow for the independent control of generation of electrons that are provided, during one or more stages of a PV waveform cycle, to neutralize the trapped charges formed in the features formed on the substrate.

In some implementations, a method for performing a plasma process in a chamber is provided, including: supplying a process gas to the chamber; applying pulsed RF power to the process gas in the chamber, the pulsed RF power being provided at a predefined frequency, wherein the applying of the pulsed RF power to the process gas generates a plasma in the chamber; during the applying of the RF power, applying a pulsed DC current to a magnetic coil that is disposed over the chamber, wherein the pulsed DC current is provided at the predefined frequency.