A plasma confinement ring includes a lower ring, an upper ring on the lower ring, and a connection ring extended to connect the lower ring to the upper ring. The lower ring includes a lower center hole vertically penetrating the lower ring at a center of the lower ring and at least one slit penetrating the lower ring in a region outside the lower center hole. The slit is structured to pass a more amount of air or gas at a first portion closer to the center of the lower ring than at a second portion farther from the center of the lower ring.

The present application provides a method for improving plasma distribution in etching, the RF coil is a circular coil composed of four arcs, and the four arcs are sequentially defined as first to fourth arcs; providing a cross support, wherein heads and tails of the first to fourth arcs are separately connected to the cross support; respectively applying different currents to the first to fourth arcs, which are sequentially first to fourth currents, so that different magnetic fields are formed respectively in areas enclosed by the first to fourth arcs and the cross support connected thereto, wherein the magnetic fields corresponding to the first to fourth currents are sequentially first to fourth magnetic fields; and adjusting the magnitudes of the first to fourth currents to change the first to fourth magnetic fields, thereby changing plasma distribution in the different areas.

There is provided a focus ring that is capable of preventing deposits from adhering to a member having a lower temperature in a gap between two members having different temperatures. A focus ring 25 is disposed to surround a peripheral portion of a wafer W in a chamber 11 of a substrate processing apparatus 10. The focus ring 25 includes an inner focus ring 25a and an outer focus ring 25b. Here, the inner focus ring 25a is placed adjacent to the wafer W and configured to be cooled; and the outer focus ring 25b is placed so as to surround the inner focus ring 25a and configured not to be cooled. Further, a block member 25c is provided in a gap between the inner focus ring 25a and the outer focus ring 25b.

A semiconductor device includes an annular semiconductor fin over a semiconductor substrate, a first bottom source/drain structure within the annular semiconductor fin, a second bottom source/drain structure surrounding the annular semiconductor fin, a first silicide layer, a second silicide layer, a first gate structure, a second gate structure, a top source/drain structure, and a contact structure over the top source/drain structure. The first silicide layer and the second silicide layer are over the first bottom source/drain structure and the bottom second source/drain structure, respectively. The first gate structure and the second gate structure are over the first silicide layer and the second silicide layer, respectively. The contact structure includes a lower contact, a middle contact over the lower contact, and an upper contact over the middle contact. A width of the upper contact is greater than a width of the middle contact.

In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.

Described examples include a method for forming an integrated circuit, the method including depositing a metal layer including aluminum and copper over a semiconductor substrate and forming a patterned photoresist layer over the metal layer. The method also including etching the metal layer to produce a patterned metal layer and ashing the patterned photoresist layer in a plasma provided in a process chamber sourced with a gas flow having an N2/O2 ratio of at least 15%.

The invention is to provide a semiconductor manufacturing apparatus system and a semiconductor device manufacturing method for reducing particles having an adverse effect in a manufacturing step of a semiconductor device. A semiconductor device manufacturing system, includes: a semiconductor manufacturing apparatus; and a platform connected to the semiconductor manufacturing apparatus via a network and in which a particle reduction processing is executed, in which the particle reduction processing includes: a step of acquiring a particle characteristic value by using a sample processed by the semiconductor manufacturing apparatus; a step of specifying a component of the semiconductor manufacturing apparatus leading to a particle generation based on the acquired particle characteristic value and correlation data by machine learning; a step of defining a cleaning condition for cleaning the semiconductor manufacturing apparatus based on the specified component; and a step of cleaning the semiconductor manufacturing apparatus using the defined cleaning condition, and the correlation data is correlation data between the particle characteristic value acquired in advance and the component.

A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.