A plasma processing device includes: a spectrometer to measure luminous intensity during plasma processing; and a control circuitry to control etching endpoint detection based on measurement results on the spectrometer. When a layered film with first layers containing silicon and oxygen and second layers containing silicon and nitrogen is etched using plasma, the first and second layers stacked alternately on top of one another and forming the layered film together, the control circuitry: acquires first luminous intensity from the spectrometer, during plasma processing, from a first wavelength range of oxygen; acquires second luminous intensity from the spectrometer, during plasma processing, from a second wavelength range of nitrogen; and detects an etching endpoint in a first layer when the first luminous intensity decreases and the second luminous intensity increases, and detects an etching endpoint in a second layer when the second luminous intensity decreases and the first luminous intensity increases.

An electrostatic chuck (ESC) for holding a workpiece in a plasma processing chamber, where the ESC includes a monolithic insulating substrate with a top surface; a plurality of electrodes embedded in the insulating substrate, the plurality of electrodes being in a multipolar configuration to receive multiple DC bias signals from a first power supply circuit; and a radio frequency (RF) electrode embedded in the insulating substrate, the plurality of electrodes being located between the top surface and the RF electrode, the RF electrode including a contact node configured to be coupled to a second power supply circuit configured to generate an RF signal.

Embodiments of the present disclosure generally relate to methods and processes to selectively deposit Si:P layers onto a semiconductor structure. More specifically, embodiments described herein provide for methods for enhancing epitaxial deposition of Si:P layers onto semiconductor structures at lower temperatures. In some embodiments, a method includes positioning a substrate within a processing volume of a processing chamber, introducing a process gas such as a silicon source and a dopant gas to the processing chamber, and forming an epitaxial layer on a surface of the substrate at a processing temperature of about 450 C. or less. The partial pressure of the silicon source is preferably about 10 Torr to about 300 Torr.

Embodiments of the present disclosure provide methods for forming semiconductor device structures. The method includes forming a fin structure from a substrate, and the fin structure includes alternating first and second semiconductor layers. The method further includes removing edge portions of each of the second semiconductor layers, depositing an insulating material around the fin structure, performing a thermal process to expand the second semiconductor layers laterally, forming a sacrificial gate structure over a portion of the fin structure, recessing an exposed portion of the fin structure, and forming a source/drain region over the recessed portion of the fin structure.

A semiconductor device has a substrate with a diamond material. A surface of the substrate is prepared using a first reaction process. The first reaction process can be etching or polishing with oxygen and methane at a gas mixture ratio of about 1:2. The surface of the substrate is exposed to hydrogen plasma prior to the first reaction process. A diamond layer is formed over the surface of the substrate using a second reaction process. The second reaction process can be nucleation or epitaxial growth. The transition from the first reaction process to the second reaction process is seamless. The transition is seamless by nature of the second reaction process continuing from the first reaction process. The diamond layer can be formed over the surface of the substrate using a third reaction process, such as an epitaxial growth. A semiconductor device is formed in the substrate and diamond layer.

Provided is a substrate processing apparatus, including a chamber including a plasma region and a processing region configured to process a substrate, a gas supply configured to supply a plasma gas to the plasma region and supply an etching gas to the processing region, a power supply configured to generate a plasma from the plasma gas, a blocker disposed between the plasma region and the processing region and configured to selectively allows radicals in the plasma to pass from the plasma region to the processing region, a shower head including a gas flow path configured to supply the etching gas to the processing region and a radical flow path configured to supply the radicals to the processing region, and a heater configured to adjust a temperature of the etching gas moving along the gas flow path or a temperature of the radicals moving along the radical flow path.

A semiconductor processing tool cluster includes: a first semiconductor processing tool including a microwave generator comprising at least one magnet and configured to perform semiconductor wafer processing using microwave energy produced by the microwave generator; a second processing tool configured to perform semiconductor wafer processing using a plasma generated in a process chamber of the second processing tool; and a magnetic field shield comprising at least one closed annular shell disposed around the microwave generator of the first semiconductor processing tool, the at least one closed annular shell comprising a material with magnetic permeability that is greater than the magnetic permeability of free space. In some cases, a magnetometer may be arranged to measure a magnetic field at a location outside of the magnetic field shield, and a circuit performs a remedial action based on a magnetic field measurement output by the magnetometer.

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

The concept relates to a method for producing a three-dimensionally integrated semiconductor memory. A layer stack having several individual layers of different material types is provided and individual layers of a first material type are etched out selectively from the layer stack by a dry etching process. Individual layers of a third material type are generated either by filling voids with a third material or converting the individual layers of the second material type into the individual layers of the third material type, or by coating the individual layers of the second material type with a material of the third material type. Voids between the individual layers of the third material type can then again be filled with a fourth material, such that individual layers of a fourth material type are formed in these voids.

The present technology encompasses plasma sources including a first plate defining a first plurality of apertures arranged in a first set of rows. The first plate may include a first set of electrodes extending along a separate row of the first set of rows. The plasma sources may include a second plate defining a second plurality of apertures arranged in a second set of rows. The second plate may include a second set of electrodes extending along a separate row of the second set of rows. Each aperture of the second plurality of apertures may be axially aligned with an aperture of the first plurality of apertures. The plasma sources may include a third plate positioned between the first plate and the second plate. The third plate may define a third plurality of apertures.