A semiconductor package includes: a package substrate, a first stack structure disposed on the package substrate, the first stack structure including first semiconductor chips stacked and connected to each other by bonding wires, a second stack structure disposed on the first stack structure, and including second semiconductor chips stacked, the second stack structure having an overhang region protruding beyond an uppermost first semiconductor chip of the first stack structure among the first semiconductor chips, an adhesive member covering a lower surface of the second stack structure and adhered to a portion of upper surfaces of the first stack structure, and an encapsulant disposed on the package substrate and covering the first stack structure and the second stack structure, wherein at least a portion of the bonding wires are buried in the die adhesive film in the overhang region to support the second stack structure.

A memory module, includes a module substrate and at least one semiconductor package on the module substrate that includes a package substrate having a lower surface and an upper surface. First and second groups of lower pads are on the lower surface, and upper pads are on the upper surface and are electrically connected to the lower pads of the first group. A chip structure is on the upper surface of the package substrate and is electrically connected to the upper pads. First connection bumps connect the lower pads of the first group to the module substrate, and second connection bumps connect the lower pads of the second group to the module substrate. The first connection bumps have a first maximum width at a first distance from the package substrate, and the second connection bumps have a second maximum width at a second, shorter distance from the package substrate.

A semiconductor package includes a package substrate, a first semiconductor chip on an upper surface of the package substrate, a spacer chip on the upper surface of the package substrate and spaced apart from the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the spacer chip by a plurality of adhesive films, respectively, and a molding member on the spacer chip, the first semiconductor chip, and the plurality of second semiconductor chips. When viewed in a plan view, the spacer chip has an overlapping region overlapping with a lowermost second semiconductor chip of the plurality of second semiconductor chips. The lowermost second semiconductor chip is attached to the spacer chip by a first adhesive film. A portion of the first adhesive film attached to the spacer chip is within a recess that is in an upper surface of the overlapping region of the spacer chip.

Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.

A semiconductor package includes a package substrate, a chip stack having first semiconductor chips stacked on the package substrate, a first molding film covering the chip stack on the package substrate, a first connection wire vertically penetrating the first molding film to be connected to the package substrate, and exposed onto an upper surface of the first molding film, a second semiconductor chip disposed on the first molding film, and having a first chip pad disposed on one surface facing the package substrate, a second molding film covering the second semiconductor chip on the first molding film, and a connection terminal connecting the first chip pad and an upper end of the first connection wire.

A semiconductor package includes: a package substrate, a first chip on the package substrate, a second chip on the package substrate and spaced apart from the first chip in a horizontal direction, a third chip having a film adhesive layer attached to a lower surface thereof, and attached to the first chip and the second chip, a first fillet adhesive layer surrounding a side surface of the first chip and in contact with a portion of the lower surface of the third chip, and a second fillet adhesive layer between the second chip and the third chip. A vertical level of an upper surface of the first chip is higher than a vertical level of an upper surface of the second chip, and the second fillet adhesive layer protrudes from the upper surface of the second chip in the horizontal direction.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.

According to one embodiment, a semiconductor device includes a semiconductor chip, a first conductor which includes a first portion exposed from a first surface of a sealing resin facing to a first direction, a second portion projecting from a second surface of the sealing resin facing to a second direction, and a bent portion connecting the first portion and the second portion, a second conductor exposed from a third surface of the sealing resin opposed to the first surface and having a thickness in the first direction which is greater than a thickness of the first conductor, a third conductor provided between the semiconductor chip and the first conductor, a first bonding material which bonds the semiconductor chip and the second conductor, a second bonding material which bonds the semiconductor chip and the third conductor, and a third bonding material which bonds the third conductor and the first conductor.