The technical idea of the inventive concept provides a semiconductor package including a package substrate including a base board layer, a plurality of conductive line patterns inside the base board layer, a plurality of conductive vias respectively connected to some of the plurality of conductive line patterns, and a plurality of lower pads disposed on a lower surface of the base board layer, respectively connected to some of the plurality of conductive vias and including at least one test lower pad to which a test signal for testing at least one of a first semiconductor chip and a semiconductor chip stack is applied, the first semiconductor chip disposed on the package substrate, and the semiconductor chip stack disposed on the package substrate. In a plan view of the semiconductor package, the at least one test lower pad is disposed between the first semiconductor chip and the semiconductor chip stack.

A semiconductor package includes a substrate including a wiring; a chip stack including a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips has upper and lower surfaces, opposite to each other, front and rear surfaces, opposite to each other, left and right surfaces, opposite to each other, and connection pads disposed on the upper surface adjacent to the front surface; bonding wires electrically connecting the connection pads to the wiring of the substrate; a plurality of attachment films disposed on the lower surface of each of the plurality of semiconductor chips; a mold layer covering the chip stack and the bonding wires; and connection bumps disposed below the substrate, and electrically connected to the wiring, wherein at least one of the plurality of attachment films covers the rear surface of at least one semiconductor chip among the plurality of semiconductor chips.

A semiconductor package includes: a package substrate including a plurality of insulating layers and a plurality of metal pattern layers respectively disposed on the plurality of insulating layers, wherein each of the plurality of metal pattern layers has an interconnection layer; at least one semiconductor chip disposed on an upper surface of the package substrate, and connected to the interconnection layer; contact pads disposed on a lower surface of the package substrate, and connected to the interconnection layer; and non-contact pads disposed on the lower surface of the package substrate, and insulated from the interconnection layer, wherein a lowermost metal pattern layer among the plurality of metal pattern layers has a first open region at least partially overlapping at least one non-contact pad among the non-contact pads, in a direction perpendicular to the upper surface of the package substrate.

A stacked semiconductor package may include a package base substrate, a first chip stack including a first semiconductor chips stacked sequentially on the package base substrate, a second chip stack including second semiconductor chips stacked sequentially on the first chip stack, and bonding wires electrically connecting the first semiconductor chips and the second semiconductor chips to the package base substrate. Each of the first semiconductor chips may be shifted by a first interval in a first horizontal direction to have a step shape. Each of the second semiconductor chips may be shifted by the first interval in a second horizontal direction, opposite to the first horizontal direction, to have a step shape. A lowermost second semiconductor chip may be shifted from an uppermost first semiconductor chip by a second interval in the second direction. The second interval may be greater than the first interval.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.

A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes circuit elements on a first substrate, a lower interconnection structure coupled with the circuit elements, and a lower bonding structure coupled with the lower interconnection structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure including interlayer insulating layers and gate electrodes, a plurality of separation regions at least partially penetrating through the stack structure, channel structures including a channel layer and at least partially penetrating through the stack structure, a plurality of address studs spaced apart from each other by a first separation distance, a plurality of channel studs below the channel structures, and an upper interconnection structure below the stack structure, coupled with the plurality of channel studs, and spaced apart from the plurality of address studs.