The present disclosure relates to a flip-chip based moisture-resistant module, which includes a substrate with a top surface, a flip-chip die, a sheet-mold film, and a barrier layer. The flip-chip die has a die body and a number of interconnects, each of which extends outward from a bottom surface of the die body and is attached to the top surface of the substrate. The sheet-mold film directly encapsulates sides of the die body, extends towards the top surface of the substrate, and directly adheres to the top surface of the substrate, such that an air-cavity with a perimeter defined by the sheet-mold film is formed between the bottom surface of the die body and the top surface of the substrate. The barrier layer is formed directly over the sheet-mold film, fully covers the sides of the die body, and extends horizontally beyond the flip-chip die.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a first dielectric layer, at least one antenna, at least one die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive circuits, a third dielectric layer, a plurality of second conductive circuits, and an outer protective layer is provided. The first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. The die is electrically connected with the antenna. The die is electrically connected to the outside through bonding pads around a chip area on a second surface of the die. Thereby the FOWLP unit is formed and problems of the FOWLP module or technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

A semiconductor package according to an embodiment includes a substrate; a protective layer disposed on the substrate; a first adhesive member disposed on the protective layer and having an open loop shape along a circumferential direction of an upper surface of the protective layer; and a cover member disposed on the first adhesive member, wherein a lower surface of the cover member includes: a first lower surface that contacts the first adhesive member, and a second lower surface that does not contact the first adhesive member, and the protective layer includes a first opening that vertically overlaps the second lower surface of the cover member and does not vertically overlap the first adhesive member.

A semiconductor device has a first semiconductor package, second semiconductor package, and RDL. The first semiconductor package is disposed over a first surface of the RDL and the second semiconductor package is disposed over a second surface of the RDL opposite the first surface of the RDL. A carrier is initially disposed over the second surface of the RDL and removed after disposing the first semiconductor package over the first surface of the RDL. The first semiconductor package has a substrate, plurality of conductive pillars formed over the substrate, electrical component disposed over the substrate, and encapsulant deposited around the conductive pillars and electrical component. A shielding frame can be disposed around the electrical component. An antenna can be disposed over the first semiconductor package. A portion of the encapsulant is removed to planarize a surface of the encapsulant and expose the conductive pillars.

An electronic device package and method of fabricating such a package includes a first and second components encapsulated in a volume of molding material. A surface of the first component is bonded to a surface of the second component. Upper and lower sets of redistribution lowers that include, respectively, first and second sets of conductive interconnects are formed on opposite sides of the molding material. A through-package interconnect passes through the volume of molding material and has ends that terminate, respectively, within the upper set of redistribution layers and within the lower set of redistribution layers.

A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a plurality of back side metallization interconnects; and a second substrate coupled to the first substrate through a first plurality of solder interconnects, wherein the second substrate is coupled to the plurality of back side metallization interconnects through the second plurality of solder interconnects.

A package substrate according to the present disclosure includes a package substrate, an interposer disposed over the package substrate, a photonic die disposed over the interposer, a memory structure disposed over the interposer and including a controller die, a system die disposed over the interposer and partially overlapping with the photonic die and the controller die, and a lid covering the system die, the memory structure, and photonic die. The system die includes micro bumps extending from a bottom surface of the system die to a top surface of the controller die.

A semiconductor package includes a package substrate having connection terminals. The connection terminals include first to fourth DQ terminals, and first and second CA terminals. A first chip stack has a first semiconductor chip flip-chip-mounted and connected to the first DQ terminals, and a fourth semiconductor chip on the first semiconductor chip wire-bonded to be connected to the fourth DQ terminals. A second chip stack has a second semiconductor chip flip-chip-mounted and connected to the second DQ terminals, and a third semiconductor chip on the second semiconductor chip wire-bonded and connected to the third DQ terminals. The first and third semiconductor chips are commonly connected to the first CA terminals, and the second and the fourth semiconductor chips are commonly connected to the second CA terminals.

A semiconductor package may include a package substrate; first semiconductor chips sequentially stacked on an upper surface of the package substrate; a second semiconductor chip on an uppermost first semiconductor chip among the first semiconductor chips, the second semiconductor chip having an overhang region protruding from one side of the uppermost first semiconductor chip and an overlapping region overlapping the uppermost first semiconductor chip, the second chip pads including first bonding pads in the overhang region and second bonding pads in the overlapping region; first conductive bumps respectively on the first bonding pads; second conductive bumps respectively on the second bonding pads; vertical wires extending from the first conductive bumps to substrate pads of the package substrate, respectively; and a molding member covering the first semiconductor chips, the second semiconductor chip, and the vertical wires.