A narrow border reflective display device includes an driving circuit substrate, a TFT substrate, a front plane laminate, multiple conductive wires, a cover, and a glue. The TFT substrate is located on the driving circuit substrate. The TFT substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the driving circuit substrate and the TFT substrate. The cover is located on the front plane laminate. The glue surrounds the driving circuit substrate, the TFT substrate, the front plane laminate, the front plane laminate, and the conductive wires.

A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

Provided is a semiconductor package including a package substrate having a first upper connection pad and a second upper connection pad provided on a top surface of the package substrate, a semiconductor chip disposed on the package substrate, a second semiconductor chip provided on the first semiconductor chip, a plurality of first chip pads and a plurality of second chip pads provided on top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, a plurality of first conductive patterns, a plurality of second conductive patterns, and a cross conductive pattern of which both ends are connected to the first conductive pattern, wherein the cross conductive pattern is provided on a top surface of the first semiconductor chip and the second conductive pattern, and the cross conductive pattern crosses the second cross conductive pattern.

A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.

A memory subsystem includes an I/O die, a host device, and a stacked memory structure. The I/O die includes a first surface and a second surface. The host device is stacked on the first surface of the I/O die to be at least partially bonded thereto. The stacked memory structure is stacked on the first surface of the I/O die to be at least partially bonded thereto. The I/O die includes a plurality of conductive pads arranged on the first surface. The stacked memory structure includes a plurality of memory dies stacked in a shingled manner so that a plurality of bonding pads is exposed, and a plurality of vertical wires respectively connecting the bonding pads of the plurality of memory dies to the plurality of conductive pads. The host device and the stacked memory structure is configured to interface with each other through the I/O die.

Stacked semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device can include a package substrate and a stack of semiconductor dies carried by the package substrate. The stack of semiconductor dies includes a first die carried by the package substrate and a second die carried by the first die. The semiconductor device also includes an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The interconnect module includes a first end coupled the package substrate, a second end opposite the first end, a conductive via extending through a body of organic material from the first end to the second end. The first semiconductor die can is electrically coupled directly to the package substrate, while the second semiconductor die is electrically coupled to the package substrate through the second end of the interconnect module.

A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

Systems and methods for measuring and predicting the strength of semiconductor devices and packaging are disclosed. In some embodiments, a semiconductor device assembly comprises a package substrate, a semiconductor die electrically coupled to the package substrate, and a molding covering at least a portion of the semiconductor die, where the molding includes a through-mold via (TMV) extending from an upper surface into the mold material to a depth. The semiconductor device assembly can include a strain gauge disposed in the molding at the depth of the TMV and be electrically coupled to the TMV. For example, the TMV can extend to the surface of the semiconductor die, to the package substrate, or other critical areas of the semiconductor device assembly, enabling strain to be measured at these depths. The semiconductor device assembly can be used in testing to predict the strength of the die and packaging in real-world scenarios, such as being dropped, bent, or crushed.

Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.

A semiconductor device includes: a wiring board having a surface; a chip stack disposed above the surface and including a first semiconductor chip; a second semiconductor chip disposed between the surface and the chip stack; a spacer disposed between the surface and the first semiconductor chip, the spacer surrounding the second semiconductor chip along the surface, and the spacer containing a material higher in thermal conductivity than silicon; and a sealing insulation layer covering the chip stack.