This application is directed to packaging technology for providing an electronic device (e.g., a memory device). A memory device includes a stack of memory chips, a device substrate, and a conductive wire. The stack of memory chips includes a first memory chip having a chip pad that is formed on a surface of the first memory chip. The device substrate includes a plurality of substrate pads formed on a front surface of the device substrate. The front surface has a front opening, and the device substrate receives the stack of memory chips via the front opening of the front surface. The conductive wire is coupled to the front surface and the stack of memory chips, and is configure to couple the chip pad and one of the substrate pads electrically. In some embodiments, the device substrate includes a cutout opening that goes through an entire thickness of the device substrate.

Stacked semiconductor packages with features to mitigate trace exposer and associated systems and methods are disclosed herein. In some embodiments, the stacked semiconductor package includes a base substrate, a stack of dies carried by the base substrate, and a mold material deposited at least partially encapsulating the stack of dies. The base substrate can include an active surface and a back surface opposite the active surface. Further, the active surface can include one or more cuts into a peripheral portion of the active surface (e.g., stepped structures at the peripheral edges of the base substrate). The base substrate can also include a plurality of bond pads carried by the active surface over the peripheral portion. Still further, the mold material can fill each of the one or more cuts in the active surface, thereby insulating the bond pads from exposure at a sidewall of the stacked semiconductor package.

A semiconductor package may include a package substrate; first semiconductor chips sequentially stacked on an upper surface of the package substrate; a second semiconductor chip on an uppermost first semiconductor chip among the first semiconductor chips, the second semiconductor chip having an overhang region protruding from one side of the uppermost first semiconductor chip and an overlapping region overlapping the uppermost first semiconductor chip, the second chip pads including first bonding pads in the overhang region and second bonding pads in the overlapping region; first conductive bumps respectively on the first bonding pads; second conductive bumps respectively on the second bonding pads; vertical wires extending from the first conductive bumps to substrate pads of the package substrate, respectively; and a molding member covering the first semiconductor chips, the second semiconductor chip, and the vertical wires.

Provided is a semiconductor device including a peripheral circuit structure comprising peripheral circuits and a cell array structure overlapping the peripheral circuit structure and comprising first and second cell array regions and a connection region therebetween in a first direction, the cell array structure including a buried insulating pattern in the connection region, the buried insulating pattern having first and second side surfaces facing each other in the first direction and a third side surface connecting the first and second side surfaces, a stack including vertically stacked conductive patterns, each of the conductive patterns including a horizontal portion parallel to the first direction and a pad portion inclined with respect to the horizontal portion, and cell contact plugs connected to the pad portions of the conductive patterns, respectively, and the pad portion of each conductive pattern being on the first, second, and third side surfaces of the buried insulating pattern.

A semiconductor package includes a package substrate having substrate pads disposed in a first direction on one surface, a semiconductor chip having chip pads disposed in the first direction, and bonding wires connecting the chip pads and the substrate pads. The bonding wires include first and second bonding wires alternately connected to the substrate pads respectively, in the first direction, the first bonding wires are connected to the substrate pads at a first angle less than a right angle with respect to a direction of the semiconductor chip, the second bonding wires are connected to the substrate pads at a second angle less than the first angle with respect to the direction of the semiconductor chip and a position at which the first bonding wires contact the substrate pads is closer to the semiconductor chip than a position at which the second bonding wires contact the substrate pads is to the semiconductor chip.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.

A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

A semiconductor device includes a cell structure including gate electrodes and mold insulating layers alternately stacked one by one in a vertical direction, a channel structure extending in the vertical direction through the gate electrodes and the insulating layers, wherein a first end portion of the channel structure protrudes upward from an uppermost mold insulating layer, and a common source layer connected to the first end portion of the channel structure and located on the uppermost mold insulating layer. The uppermost mold insulating layer includes a first low-refractive-index layer on a lower surface of the common source layer, a high-refractive-index layer on a lower surface of the first low-refractive-index layer, and a second low-refractive-index layer on a lower surface of the high-refractive-index layer.

A method of fabricating a semiconductor device may include forming a lower mold structure on a substrate, forming a first mold structure on the lower mold structure, the first mold structure including first interlayer insulating layers and first sacrificial layers, which are alternately stacked in a vertical direction, forming first vertical channel holes to penetrate the first mold structure, the lower mold structure, and a portion of the substrate, and forming an active layer to cover a top surface of the first mold structure and extend to an upper side surface of each of the first vertical channel holes. The active layer may include a horizontal portion covering the top surface of the first mold structure and a vertical portion covering the upper side surface of each of the first vertical channel holes, and the active layer may include a metallic material.