Provided is an electronic device, in which a first management module of a first chiplet generates a first request transaction for measuring a latency between the first chiplet and a second chiplet, and transmits the generated first request transaction to the second chiplet through a first interconnect module of the first chiplet, a second management module of the second chiplet generates a first response transaction corresponding to the first request transaction, and transmits the generated first response transaction to the first chiplet through a second interconnect module of the second chiplet, and the latency between the first chiplet and the second chiplet is determined based on a first time at which the first request transaction is generated in the first chiplet and a second time at which the first chiplet receives the first response transaction.

A semiconductor package includes a number of different substrate sections. Each substrate section includes one or more electronic components. Additionally, each substrate section is mechanically and electrically coupled together using various conductive columns and conductive apertures. Because the substrate sections are interconnectable, a shape and/or a size of the semiconductor package is fully customizable. Additionally, a layout of the various electronic components of the semiconductor package is also fully customizable.

A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts with a first average pitch, a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts with a second average pitch, and a signal routing structure between the first and second semiconductor devices and including a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a pattern of parallel conductive lines between the first and second pluralities of conductive structures. The pattern of parallel conductive lines has a third average pitch less than the first and second average pitches, and pairs of conductive structures from the first and second pluralities are electrically coupled by different ones of the parallel conductive lines.

A layout without bridge taps includes: a routing from a CPU to a first module through a first set of pads; a routing from a first set of bridge pads to a second module through a second set of pads and a second set of bridge pads; a routing from a third set of pads to a third module; and connectors. The connectors connect pads of the first set of pads to couple the CPU with the first module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the second set of bridge pads to couple the CPU with the second module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the third set of pads to couple the CPU with the third module.

Provided is an electronic device, in which a first management module of a first chiplet generates a first request transaction for measuring a latency between the first chiplet and a second chiplet, and transmits the generated first request transaction to the second chiplet through a first interconnect module of the first chiplet, a second management module of the second chiplet generates a first response transaction corresponding to the first request transaction, and transmits the generated first response transaction to the first chiplet through a second interconnect module of the second chiplet, and the latency between the first chiplet and the second chiplet is determined based on a first time at which the first request transaction is generated in the first chiplet and a second time at which the first chiplet receives the first response transaction.

An electronic device includes a substrate, an outer layer, a conductive line layer, and a switchable circuit chip. The substrate has a plurality of having a plurality of first vias. The outer layer is disposed on a side of the substrate and has a plurality of second vias. The first vias have a larger distribution density or quantity than the second vias, so that a part of the first vias are electrically connected to the second vias, and another part of the first vias are electrically floating. The conductive line layer is disposed on the outer layer and has a plurality of conductive traces. The conductive traces are electrically connected to the second vias. The switchable circuit chip is electrically connected to the first vias. The conductive traces are electrically connected to the switchable circuit chip. The switchable circuit chip is configured for controlling an electrical connecting relationship between the conductive traces and the first vias and an electrical connecting relationship among the conductive traces.

The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

Provided is an electronic device, including a first chiplet including a system bus, a first interconnect module, and a second interconnect module, and a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or second interconnect interface connected to the second interconnect module, in which, in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed.