The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes stacked first and second chips, a local word line decoder and a local bit line decoder for controlling an array block are disposed in the second chip, and the first chip forms an electrical connection with the second chip. At least one of the local word line decoder block and the local bit line decoder block formed by the local word line decoder block and the local bit line decoder block respectively is arranged within the top-down projection region of the array block in the second chip.

A method of manufacturing a semiconductor package includes: hybrid-bonding a semiconductor chip, including a through-silicon via, to an upper surface of a semiconductor wafer, wet-etching a surface of the semiconductor chip to expose the through-silicon via, covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer, removing an upper surface of the encapsulation layer to expose the through-silicon via, and forming a redistribution structure electrically connected to the through-silicon via.

A first side of a sensor wafer is bonded to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation that enters the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer contains circuitry configured to operate the pixels. The sensor wafer or the first logic wafer contains a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. A through-substrate-via (TSV) is formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from being damaged during the forming of the TSV. The second side of the first logic wafer is bonded to a second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

A holding head structure and a manufacturing method using the same are disclosed. The holding head structure includes a body of a matrix material, a plurality of operating cores embedded in the matrix material of the body, and a plurality of isolators in the body and defining holding units. The holding units are electrically isolated from one another by the plurality of isolators. Each holding unit includes at least one operating core, and each holding unit is configured to be individually controlled and be electrically connected to a power source.

A wafer processing method is disclosed. A second wafer is bonded to a first wafer. An undercut region is formed along the periphery of a front surface of the second wafer. A grinding process is performed on a back surface of the second wafer, thereby thinning the second wafer to a predetermined thickness.

There is provided a memory device including a first chip including a first normal region, the first region including a plurality of first normal connectors on a first surface and configured to be provided with signals used during an operation of memory cells, and a first test region including a plurality of first connectors on the first surface and electrically connected to each other, and a second chip. The second chip includes a second normal region including a plurality of second normal connectors, and configured to provide signals used during the operation of the memory cells to the first normal connectors, and a second test region including a plurality of first and second test connectors on the second surface so as not to overlap the plurality of first connectors in the first direction, and configured to not be provided with signals used during the operation of the memory cells.

A device structure includes at least one alternating stack of respective layers and electrically conductive layers, a memory opening vertically extending through each layer within the at least one alternating stack, a memory opening fill structure located in the memory opening, and a contact via structure in contact with a first electrically conductive layer of the electrically conductive layers. An outer blocking dielectric layer contacts the first electrically conductive layer, laterally surrounds the contact via structure, and vertically extends continuously through the alternating stack and the at least one retro-stepped dielectric material portion.

A method for forming a semiconductor structure for wafer level bonding includes the steps of forming a bonding dielectric layer on a substrate, forming an opening in the bonding dielectric layer, wherein an bottom angle between a sidewall and a bottom surface of the opening is smaller than 90 degrees, forming a conductive material layer on the bonding dielectric layer and filling the opening, and performing a chemical mechanical polishing process to remove the conductive material layer outside the opening, thereby forming a bonding pad in the opening.

The present technology relates to hybrid bonding of semiconductor memory wafer and semiconductor CMOS wafer using one or more debondable carriers. In one embodiment, a semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor wafer having complementary metal-oxide-semiconductor (CMOS) transistor devices, the first semiconductor wafer having a first frontside surface and a first backside surface, and a second semiconductor wafer having one or more memory arrays, the second semiconductor wafer having a second frontside surface and a second backside surface, wherein a bonding interface is formed between the first backside surface of the first semiconductor wafer and the second frontside surface of the second semiconductor wafer, and wherein the first semiconductor wafer has a first dielectric layer disposed on its first frontside surface.

Systems, devices, and methods for high die stack packages with vertical die-to-die interconnects are provided herein. A die stack package can include a substrate, a lower die stack carried by the substrate, a spacer carried by the substrate, an upper die stack carried by the spacer, a plurality of wire bonds, and a plurality of vertical wires. The lower die stack can include a plurality of lower dies stacked in a cascading arrangement. The upper die stack can include a plurality of upper dies stacked in a cascading arrangement in a same direction as the plurality of lower dies. The wire bonds can electrically couple adjacent ones of the lower dies. An nth vertical wire can extend vertically between and electrically couple an nth upper die and an nth lower die. In some embodiments, the die stack package further includes an input-and-output extender carried by the substrate.