A method of processing a semiconductor element is disclosed. The method can include providing the semiconductor element that has a first nonconductive material. The first nonconductive material is disposed on a device portion of the semiconductor element. The method can include providing a transparent carrier. The method can include providing an intervening structure that has a second nonconductive material, a photolysis layer, and an opaque layer stacked together. The method can include forming a bonded structure such that the second nonconductive material is directly bonded to the first nonconductive material or to the transparent carrier. The intervening structure is disposed between the semiconductor element and the transparent carrier. The method can include decoupling the transparent carrier from the semiconductor element by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.

A method for forming a semiconductor assembly that includes forming a first set of layers on a first wafer, where one or more layers of the first set includes one or more devices of the semiconductor assembly. The method further includes forming a second set of layers on a second wafer, where one or more layers of the second set include connections between one or more of the devices of the semiconductor assembly. The method additionally includes coupling a layer of the first set to a layer of the second set using metal to metal hybrid bonding.

A semiconductor device includes a first substrate. The semiconductor device includes a plurality of metallization layers formed over the first substrate. The semiconductor device includes a plurality of via structures formed over the plurality of metallization layers. The semiconductor device includes a second substrate attached to the first substrate through the plurality of via structures. The semiconductor device includes a first conductive line disposed in a first one of the plurality of metallization layers. The first conductive line, extending along a first lateral direction, is connected to at least a first one of the plurality of via structures that is in electrical contact with a first through via structure of the second substrate, and to at least a second one of the plurality of via structures that is laterally offset from the first through via structure.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The third semiconductor layer is between the second peripheral circuit and the second bonding interface.

A semiconductor device includes: a lower semiconductor structure including one or more first lower test pads, one or more second lower test pads that are alternately arranged with the one or more first lower test pads, and a lower test terminal that is electrically connected to the second lower test pad through a second lower test line; and an upper semiconductor structure positioned over the lower semiconductor structure and including an upper test pad and an upper test terminal that is electrically connected to the upper test pad through an upper test line, wherein, when the lower semiconductor structure and the upper semiconductor structure are aligned, the upper test pad overlaps with and contacts a corresponding first lower test pad among the one or more first lower test pads, and is spaced apart from the second lower test pad that is adjacent to the corresponding first lower test pad.

A semiconductor package may include a substrate including a plurality of vias and a chip stack on the substrate. The chip stack may include a plurality of semiconductor chips, wherein a first semiconductor chip is a lowermost one of the plurality of semiconductor chips in the chip stack, chip pads of the first semiconductor and substrate pads of the substrate are bonded to each other, and the chip pads and the substrate pads are integrally formed of the same metal material, the first semiconductor chip includes a corner region adjacent to a corner of the first semiconductor chip, and a center region excluding the corner region, the substrate includes a trench on an upper surface of the substrate, and the trench extends along a boundary between the corner region and the center region of the first semiconductor chip.

Embodiments of multi-chamber processing tools are provided herein. In some embodiments, a multi-chamber processing tool includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; a plurality of atmospheric modular mainframes coupled to each other and having a first atmospheric modular mainframe coupled to the EFEM, wherein each of the plurality of atmospheric modular mainframes include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein at least one of the plurality of atmospheric modular mainframes includes a bonder chamber, wherein the transfer chamber includes a buffer having a plurality of shelves for supporting the one or more types of substrates and includes a transfer robot; and an atmospheric plasma activation module disposed in the transfer chamber or one of the one or more process chambers.

A microelectronic device includes a control logic structure including a high-power component. The microelectronic device also includes a memory array structure vertically offset from and attached to the control logic structure, the memory array structure comprising an array of memory cells. The microelectronic device further includes a heat sink structure vertically underlying and horizontally overlapping the high-power component, the heat sink structure comprising a material having higher thermal conductivity than semiconductor material of the control logic structure.

Provided are a semiconductor chip, a semiconductor package including the same, and a method for manufacturing the same. This semiconductor chip includes a first logic die, first memory dies arranged side by side in a first direction on the first logic die, and a first mold layer between the first memory dies. The first memory dies and the first mold layer are in contact with an upper surface of the first logic die, each of the first memory dies includes first memory bank regions arranged side by side in a second direction intersecting the first direction, and the first logic die includes first core regions overlapping the first memory bank regions, respectively, in a third direction that is perpendicular to the first and second directions.

A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.