The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes stacked first and second chips, a local word line decoder and a local bit line decoder for controlling an array block are disposed in the second chip, and the first chip forms an electrical connection with the second chip. At least one of the local word line decoder block and the local bit line decoder block formed by the local word line decoder block and the local bit line decoder block respectively is arranged within the top-down projection region of the array block in the second chip.

The semiconductor structure includes a die structure including: a substrate, a first dielectric disposed over the substrate, a first interconnect structure disposed within the first dielectric, a second dielectric disposed on the first dielectric, and a conductive pad surrounded by the second dielectric; a capping member surrounding the die structure; and an insulating member surrounding the capping member, wherein the capping member includes a first oxynitride layer in contact with the die structure or the insulating member.

A first side of a sensor wafer is bonded to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation that enters the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer contains circuitry configured to operate the pixels. The sensor wafer or the first logic wafer contains a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. A through-substrate-via (TSV) is formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from being damaged during the forming of the TSV. The second side of the first logic wafer is bonded to a second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

The invention provides an integrated circuit device and an adaptive power scaling method thereof to reduce and optimize power consumption. The integrated circuit device includes a first die and a second die, wherein the first die and the second die are stacked into a three-dimensional structure. A power circuit provides a power voltage to a first interface circuit of the first die and a second interface circuit of the second die. The first interface circuit transmits data to the second interface circuit via a die-to-die transfer circuit. The control logic controls the power circuit to adjust the power voltage provided to the first interface circuit and the second interface circuit based on the signal quality of the data received by the second interface circuit.

A semiconductor device may include a source structure; a gate structure including conductive layers and insulating layers that are alternately stacked; a first channel layer including a first penetration portion extending through the gate structure and a first tip having a smaller width than the first penetration portion and protruding into the source structure; a second channel layer including a second penetration portion extending through the gate structure and a second tip having a smaller width than the second penetration portion and protruding into the source structure; and a slit structure extending through the gate structure, wherein the first tip and the second tip may have different heights.

Disclosed herein are methods of forming a microelectronic component. In some embodiments, the method includes providing an element having a metallization layer that comprises a field dielectric and a conductive feature embedded in the field dielectric. The metallization layer also comprises a surface that includes the field dielectric and the conductive feature. The method further includes forming a copper feature over the conductive feature, forming a dielectric layer over sidewalls of the copper feature, and then planarizing the dielectric layer to form a hybrid bonding surface, where the copper feature is exposed at the hybrid bonding surface.

A memory includes a stacked body including electrode layers and first insulating layers stacked in a first direction. Each of a plurality of first columnar bodies includes a semiconductor layer located to penetrate through the stacked body in the first direction. A source is connected to an end part of the semiconductor layer on a side of one end of the semiconductor layer. A pillar portion is located to extend in the first direction in the stacked body, or in a structure located alongside the stacked body in a second direction, and includes a carbon material. A cap portion is located at an end part of the pillar portion on a side of another end out of one end and another end of the pillar portion respectively corresponding to the one end and another end of the semiconductor layer, and includes a first material having an etching-selectivity to the carbon material and the first insulating films.

There is provided a memory device including a first chip including a first normal region, the first region including a plurality of first normal connectors on a first surface and configured to be provided with signals used during an operation of memory cells, and a first test region including a plurality of first connectors on the first surface and electrically connected to each other, and a second chip. The second chip includes a second normal region including a plurality of second normal connectors, and configured to provide signals used during the operation of the memory cells to the first normal connectors, and a second test region including a plurality of first and second test connectors on the second surface so as not to overlap the plurality of first connectors in the first direction, and configured to not be provided with signals used during the operation of the memory cells.

A device structure includes at least one alternating stack of respective layers and electrically conductive layers, a memory opening vertically extending through each layer within the at least one alternating stack, a memory opening fill structure located in the memory opening, and a contact via structure in contact with a first electrically conductive layer of the electrically conductive layers. An outer blocking dielectric layer contacts the first electrically conductive layer, laterally surrounds the contact via structure, and vertically extends continuously through the alternating stack and the at least one retro-stepped dielectric material portion.

A three-dimensional integrated circuit memory device includes a substrate having layers vertically stacked thereon; the layers include: memory cells horizontally arranged to form one row, a word line electrically connected to the plurality of memory cells, and an electrode horizontally extending from the word line and forming a stair structure with other electrodes associated with respective ones of the plurality of layers. Vertically-extending contacts are provided, which electrically contact corresponding electrodes in an open area of each of the layers. A first sub-word line driver has a first driving characteristic and is electrically connected through a first one of the vertically-extending contacts to an electrode associated with a first layer layers. A second sub-word line driver has a second driving characteristic different from the first driving characteristic and is electrically connected through a second one of the vertically-extending contacts to an electrode associated with a second layer among the layers.