Embodiments of the present disclosure provide an integrated circuit component, a processor, and a system on chip. The integrated circuit component includes three wafer layers. Each of the wafer layers includes a front side and a back side. The front side of a first wafer layer and the front side of a second wafer layer are stacked, and the front side of the second wafer layer and the back side of a third wafer layer are stacked. The three wafer layers are interconnected through a through-silicon via, a re-distribution layer, and hybrid bonding. The second wafer layer or a slow wafer layer among the three wafer layers includes a direct memory access master controller. The direct memory access master controller is configured to receive a data transmission request sent by a slave terminal of another wafer layer, and cause a slave terminal of the second wafer layer or the slow wafer layer among the three wafer layers to perform data transmission.

A method of forming a bonding contact, a bonding structure and a semiconductor device are disclosed. The method includes forming a bonding layer. The bonding layer comprises a central region and a peripheral region. A second conductive material layer is deposited onto the surface of the bonding area, forming a capping layer. The second conductive material layer is a different conductive material from a first conductive material layer. A portion of the capping layer in the central region is removed to expose the first conductive material layer, thereby forming the bonding contact having the remaining portion of the capping layer.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.

A semiconductor memory device includes a substrate, a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern extending in a first horizontal direction above the substrate, and spaced apart from each other, the first semiconductor pattern comprising a channel region, a source region, and a drain region, the channel region, source region, and drain region arranged in the first horizontal direction with the channel region therebetween, a first word line and a second word line, the first word line and the second word line extending in the second horizontal direction above the first semiconductor pattern, and spaced apart from each other in the vertical direction, a bit line connected to the source region of the first semiconductor pattern, and the bit line extending in the vertical direction, and a cell capacitor connected to the drain region of the first semiconductor pattern.

A memory includes a first semiconductor structure. The first semiconductor structure includes an active pillar row, a word line, a data storage element, and a first contact plug. The active pillar row includes multiple active pillars. The multiple active pillars include a first active pillar located in a first region and a second active pillar located in a second region. The second region is located on at least one side of the first region. The word line is coupled to the multiple active pillars. The data storage element is coupled to the first active pillar. The first contact plug and is coupled to the word line. An orthographic projection of the first contact plug in the first direction overlaps with an orthographic projection of the second active pillar in the first direction.

Examples of the present application provide a semiconductor structure and a fabrication method thereof, relate to the field of semiconductor chip technologies, and aim to stack more device layers in a semiconductor structure and in turn increase the number of the device layers packaged in the semiconductor structure. The semiconductor structure provided by an example of the present application includes a plurality of stack layers that are stacked and a first bonding structure, wherein two adjacent stack layers are connected together through the first bonding structure; the stack layer includes a plurality of device layers that are stacked and a second bonding structure with two adjacent device layers connected through the second bonding structure. After connecting device layers together through the second bonding structure, the thickness of the device layers can be reduced.

Bonded die structures and methods of fabricating bonded die structures including improved positioning of the dies used to form the structures. Improved positioning may be achieved by providing non-linear alignment features around the periphery of the dies that may facilitate accurate positioning of the dies with respect to one or more alignment marks on the target structures on which the dies are placed. The non-linear alignment features may include features formed in the peripheral edges of the dies, such as indent portions extending inwardly from the peripheral edges of the dies and/or outward bulge portions extending outwardly from the peripheral edges of the dies. Alternatively, or in addition, the non-linear alignment features may be features formed in a seal ring structure of the dies. The non-linear alignment features may improve the accuracy of the positioning of the dies relative to alignment mark(s) on the target structures using optical detection systems.

A semiconductor structure including a semiconductor substrate, an interconnect structure and a bonding structure is provided. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes an interconnect wiring distributed on a top surface of the interconnect structure. The bonding structure is disposed on and electrically connected to the interconnect structure. The bonding structure includes a bonding dielectric structure and a bonding conductor. The bonding dielectric structure is disposed on the top surface of the interconnect structure and covers the interconnect wiring. The bonding conductor is embedded in the bonding dielectric structure, wherein the bonding conductor lands on the top surface of the interconnect wiring and a first sidewall of the interconnect wiring.

A device comprises a first substrate directly hybrid bonded to a second substrate. The first substrate comprises at least one first conductive feature on at least one optical device material stack disposed in a first dielectric layer. The second substrate comprises at least one second conductive feature disposed in a second dielectric layer. A thickness of the at least one first conductive feature is less than about 300 nm, and a thickness of the at least one optical device material stack is greater than about 2 microns.

An example of a semiconductor package includes a buffer die having a first planarize area, a memory die stack structure including middle core dies and a top core die stacked on the buffer die in a vertical direction and having a second planar area smaller than the first planar area, an adhesion layer contacting an upper surface of the memory die stack structure, a dummy die contacting the adhesion layer and having a third planar area greater than the first planar area, and a molding structure under the dummy die and covering sidewalls of the buffer die, the memory die stack structure and the adhesion layer.