A semiconductor structure may be provided by forming a first molding compound around a first semiconductor die such that a top surface of the first molding compound is coplanar with a top dielectric surface of the first semiconductor die; forming a combination of at least one bonding-level dielectric layer, first bonding pads, and dummy pads over the first semiconductor die and the first molding compound, wherein each of the bonding pads is formed directly on a respective conductive structure within the first semiconductor die; and attaching a second semiconductor die including second bonding pads therein to the first semiconductor die by performing a bonding process that bonds the second bonding pads to the first bonding pads by metal-to-metal bonding such that a first subset of the dummy pads has an areal overlap in a plan view with the second semiconductor die.

Disclosed herein are related to a device comprising a memory chip, another memory chip, and a circuit chip between the memory chip and the another memory chip, where the circuit chip is connected to the memory chip and the another memory chip through different connections. The memory chip may include a first memory array and a first bond pad, and the another memory chip may include a second memory array and a second bond pad. The circuit chip may include a third bond pad on a first surface of the circuit chip coupled to the first bond pad, and a fourth bond pad on a second surface of the circuit chip coupled to the second bond pad. The circuit chip may include a transistor coupled to the third bond pad through a front side connection and another transistor coupled to the fourth bond pad through a backside connection.

A semiconductor memory device includes a bit line extending in a first horizontal direction and including a contact, a first channel structure and a second channel structure, each arranged to be spaced apart from one another in the first horizontal direction on the bit line and the first channel structure including a first channel pattern, a first channel pad portion, and a first channel extension portion, the second channel structure including a second channel pattern, a second channel pad portion, and a second channel extension portion, and a first word line and a second word line each extending in a second horizontal direction orthogonal to the first horizontal direction and arranged adjacent to a respective channel pattern of the first channel structure and the channel pattern of the second channel structure.

A microelectronic interconnect structure having a pre-formed hybrid bonding layer is disclosed. The hybrid bonding layer is formed over a temporary carrier comprising a substantially flat upper surface. A routing structure comprising a device or metallization layers is then provided over the hybrid bonding layer. After the hybrid bonding layer coupled with the routing structure is properly reinforced, the temporary carrier is removed to reveal a bonding surface of the hybrid bonding layer. The interconnect structure can comprise an organic dielectric material interspersing the hybrid bonding layer and forming part of the routing structure, and as such exhibit bending flexibility.

Various aspects of the present disclosure generally relate to a bonding pad configuration. A device includes a die including multiple bonding pads, pad configuration circuitry, and control circuitry. The pad configuration circuitry is configured to, based on a routing configuration, selectively connect multiple nodes of first circuitry to a first set of bonding pads of the multiple bonding pads. The control circuitry is connected to the pad configuration circuitry and configured to obtain the routing configuration.

A semiconductor package having one or more bifacial NAND memory devices includes an interposer including a plurality of multiplexers (MUX) integrally formed within the interposer, and a plurality of bifacial NAND memory devices disposed over the interposer. The bifacial NAND memory devices are electrically coupled to the MUX. Each bifacial NAND memory device includes a first NAND memory die disposed on a first planar surface, and a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, and adjacent the interposer. Each bifacial NAND memory device also includes a plurality of through silicon vias (TSVs) electrically coupling the first NAND memory die with the second NAND memory die, and the MUX.

A package structure, an assembly structure and a manufacturing method are provided. The package structure includes a molded structure, a logic device, a non-volatile memory device and a volatile memory device. The molded structure includes a memory controller device, an interconnection device and an encapsulant encapsulating the memory controller device and the interconnection device. The logic device is electrically connected to the interconnection device. The non-volatile memory device and the volatile memory device are electrically to the logic device through the memory controller device. The volatile memory device is electrically connected to the non-volatile memory device through the memory controller device.

A package structure, an assembly structure and a manufacturing method are provided. The package structure includes a molded structure, a logic device, a non-volatile memory device and a volatile memory device. The molded structure includes a memory controller device, an interconnection device and an encapsulant encapsulating the memory controller device and the interconnection device. The logic device is electrically connected to the interconnection device. The non-volatile memory device and the volatile memory device are electrically to the logic device through the memory controller device. The volatile memory device is electrically connected to the non-volatile memory device through the memory controller device.

The present invention can be applied to a technical field regarding a display device, and relates to, for example, a display device using a micro light-emitting diode (LED) and a module-type display device using same. The display device of the present invention may comprise: a first substrate comprising a first electrode placed on a first surface and a second electrode placed on a second surface and electrically connected to the first electrode; a second substrate placed on the first substrate and comprising a connection wire that defines multiple individual pixel regionsthe second substrate being placed on the first substrate so as to have an exposure part through which at least a part of the first electrode of the first substrate is exposed; a connection electrode connecting the first electrode of the first substrate to the connection wire of the second substrate while being in contact with the exposure part; and light-emitting diodes connected to the connection wire of the second substrate.

An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.