A method of manufacturing a display device includes forming a thin film transistor layer in an active area of a substrate, forming a metal layer on an edge area of the substrate, transferring first coating patterns to the edge area, the first coating patterns covering a portion of the metal layer corresponding to shapes of side surface lines, etching the metal layer to form the side surface lines, an upper surface of each of the side surface lines being covered by the first coating patterns, transferring a second coating pattern to the edge area, the second coating pattern covering a side surface of each of the side surface lines and the first coating patterns, and transferring light emitting elements to the thin film transistor layer. The second coating pattern includes openings corresponding to the first coating patterns in a plan view.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

A semiconductor device includes a first substrate. The semiconductor device includes a plurality of metallization layers formed over the first substrate. The semiconductor device includes a plurality of via structures formed over the plurality of metallization layers. The semiconductor device includes a second substrate attached to the first substrate through the plurality of via structures. The semiconductor device includes a first conductive line disposed in a first one of the plurality of metallization layers. The first conductive line, extending along a first lateral direction, is connected to at least a first one of the plurality of via structures that is in electrical contact with a first through via structure of the second substrate, and to at least a second one of the plurality of via structures that is laterally offset from the first through via structure.

A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The third semiconductor layer is between the second peripheral circuit and the second bonding interface.

A semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.

A semiconductor device includes: a lower semiconductor structure including one or more first lower test pads, one or more second lower test pads that are alternately arranged with the one or more first lower test pads, and a lower test terminal that is electrically connected to the second lower test pad through a second lower test line; and an upper semiconductor structure positioned over the lower semiconductor structure and including an upper test pad and an upper test terminal that is electrically connected to the upper test pad through an upper test line, wherein, when the lower semiconductor structure and the upper semiconductor structure are aligned, the upper test pad overlaps with and contacts a corresponding first lower test pad among the one or more first lower test pads, and is spaced apart from the second lower test pad that is adjacent to the corresponding first lower test pad.

A three dimensional semiconductor device stack includes a first non-volatile memory array device, a second non-volatile memory array device, and a functional device. The first non-volatile memory array device includes a plurality of planes. The second non-volatile memory array device included a plurality of planes. The functional device is electrically connecting to the first non-volatile memory array device and the second non-volatile memory array device. The functional device includes a z-direction switch and a plane switch. The z-direction switch is configured to select one of the first non-volatile memory array device and the second non-volatile memory array device, and the plane switch is configured to select one of the planes of the selected first non-volatile memory array device or the selected second non-volatile memory array device. A method of operating the three dimensional semiconductor device stack is also disclosed.

A semiconductor device may include a gate structure including alternately stacked insulating layers and conductive layers, a slit structure extending through the gate structure, a channel layer extending through the gate structure, a first data storage layer surrounding the channel layer, second data storage patterns respectively positioned between the conductive layers and the first data storage layer, first blocking patterns respectively positioned between the conductive layers and the second data storage patterns, and buffer patterns positioned between the insulating layers and the first data storage layer.

A semiconductor package may include a substrate including a plurality of vias and a chip stack on the substrate. The chip stack may include a plurality of semiconductor chips, wherein a first semiconductor chip is a lowermost one of the plurality of semiconductor chips in the chip stack, chip pads of the first semiconductor and substrate pads of the substrate are bonded to each other, and the chip pads and the substrate pads are integrally formed of the same metal material, the first semiconductor chip includes a corner region adjacent to a corner of the first semiconductor chip, and a center region excluding the corner region, the substrate includes a trench on an upper surface of the substrate, and the trench extends along a boundary between the corner region and the center region of the first semiconductor chip.