A semiconductor device includes a substrate, an interlayer dielectric layer, spacer structures, a gate insulating layer, a first work function metal layer and a metal gate. The interlayer dielectric layer is disposed above the substrate. The spacer structures are located in a trench of the interlayer dielectric. The gate insulating layer is disposed between inner sidewalls of the spacer structures. The gate insulating layer includes a first region doped with dipole dopant and second regions without the dipole dopant. The first region is connected with the second regions. The first region is horizontally located between the first work function metal layer and the spacer structures. The metal gate is disposed above the first work function metal layer. The metal gate is disposed between and in contact with the second regions.

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.

Methods for depositing a titanium aluminum carbide (TiAlC) film structure on a substrate are disclosed. The methods may include: depositing a first TiAlC film on a substrate utilizing a first cyclical deposition process, and depositing a second TiAlC film over the first TiAlC film utilizing a second cyclical deposition process. Semiconductor structures including titanium aluminum carbide (TiAlC) film structures deposited by the methods of the disclosure are also disclosed.

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.

The invention provides a semiconductor structure comprising a thin film resistor layer, which comprises a metal gate, wherein the metal gate comprises a titanium nitride layer, a titanium layer and an aluminum layer stacked from bottom to top, wherein the ratio of the thickness of the aluminum layer to the thickness of the titanium layer is greater than 0.66, and a thin film resistor layer is located in a dielectric layer directly above the metal gate, wherein at least a part of the thin film resistor layer and the metal gate are overlapped from a top view. The invention has the function of reducing the probability of copper extrusion in the P-type gate structure and improving the quality of semiconductor devices.

In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

The present disclosure describes a semiconductor device with modulated gate structures and a method for forming the same. The method includes forming a fin structure, depositing a polysilicon layer over the fin structure, and forming a photoresist mask layer on the polysilicon layer. The method further includes etching, with a first etching condition, the polysilicon layer not covered by the photoresist mask layer and above a top surface of the fin structure. The method further includes etching, with a second etching condition, the polysilicon layer not covered by the photoresist mask layer and below the top surface of the fin structure, where the etched polysilicon layer below the top surface of the fin structure is narrower than the etched polysilicon layer above the top surface of the fin structure. The method further includes removing the etched polysilicon layer to form a space and forming a gate structure in the space.

A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.

A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

FET designs, and in particular NMOSFET designs based on SOI fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments include FETs in which the threshold voltage V.sub.TE of the edge FETs is increased to a level that is at least equal to the threshold voltage V.sub.TC of the central conduction channel FET using a novel dual work function configuration of a high dielectric constant (high-) replacement metal gate (RMG) structure. One embodiment encompasses a FET including an RMG structure overlying a doped silicon region, the RMG structure including: an interface insulator formed over the doped silicon region; a high-K material formed over the interface insulator; an N-type work function material overlaying and in contact with a central portion of the high- material; and a P-type work function material overlaying and in contact with at least one edge portion of the high- material.