A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

According to an embodiment of the present invention, a semiconductor device includes a substrate. A plurality of nanosheets are located parallel to the substrate. A first dielectric bar extends upwards from the substrate through the plurality of nanosheets. The plurality of nanosheets extend laterally from sidewalls of the first dielectric bar. A high-k dielectric metal on a frontside surface and a backside surface of each nanosheet in the plurality of nanosheets and on the sidewalls of the first dielectric bar. A work function metal on a frontside surface, a backside surface, and exposed sidewalls of the high-k dielectric metal. A conductive metal fill between the work function metal. The conductive metal fill connecting to a sidewall of the work function metal.

The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

The present invention relates to a substrate processing method, and more particularly, to a processing method for substrate for removing impurities from inside a thin film of a substrate and improving characteristics of the thin film.

The present invention relates to a substrate processing method, and more particularly, to a processing method for substrate for removing impurities from inside a thin film of a substrate and improving characteristics of the thin film.

Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions.

A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.

The present disclosure provides a method for manufacturing a semiconductor device using selective vapor deposition and selective desorption. The method for manufacturing a semiconductor device includes providing a first layer having a first surface, and forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer. The second layer has a second surface that meets the first surface. An inhibitor layer is formed on the first surface and the second surface, and the inhibitor layer on the second surface is selectively removed to expose the second surface. An interest layer is formed on the second surface. Physical properties of the first layer are different from physical properties of the second layer.

Described herein is a technique capable of suppressing the generation of particles due to a film peeling in a process chamber. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) loading a substrate with an oxide film formed thereon into a process chamber wherein a metal-containing film is formed on a wall or other location in the process chamber; (b) supplying into the process chamber with at least one among: a gas containing a group 14 element and hydrogen; and a gas containing oxygen; and (c) forming the metal-containing film on the substrate after (b).

A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.