According to one embodiment, a semiconductor chip includes a first electrode, a semiconductor layer, a second electrode, a third electrode, and a metallic layer. The semiconductor layer includes a first portion, a second portion, and a third portion that is located between the first portion and the second portion. The semiconductor layer is provided on a first side of the first electrode in a first direction. The second electrode is over the first portion in the first direction. The third electrode is over the second portion in the first direction. The metallic layer is provided on a second side of the first electrode and is under the third portion in the first direction.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.

A semiconductor package comprises a base substrate, a first semiconductor chip on the base substrate, a first dam structure which overlaps a corner of the first semiconductor chip from a plan view and is placed on the base substrate and a first fillet layer which is placed vertically between the base substrate and the first semiconductor chip, and vertically between the first dam structure and the first semiconductor chip.

Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. More specifically, there may be provided includes a display device including an adhesive layer which includes a first portion and a second portion, wherein the first portion has higher adhesion than the second portion, and the second portion has lower adhesion than the first portion and includes high refractive particles so that a manufacturing process is simplified, and a method of manufacturing the same.

A bonded substrate structure includes a first substrate; a second substrate; and a bonding region bonding the first substrate to the second substrate. The bonding region includes an aluminum oxide bonding layer directly contacting an aluminum nitride layer, and a bonding interface between the aluminum oxide bonding layer and a bonding surface of the first substrate or the second substrate.

A semiconductor package may include a base chip, at least one chip stack module on the base chip, and a sealant on the base chip and sealing the at least one chip stack module. The at least one chip stack module may have an integral structure, in which a plurality of memory chips may be stacked and uniform. Each chip stack module of the at least one chip stack module may be on the base chip while having the integral structure.

A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

A display panel includes a circuit substrate, pixel structures and a molding layer. The circuit substrate has first pad structures and second pad structures. The pixel structures are disposed above a display region of the circuit substrate. Each of at least a portion of the pixel structures includes a first light emitting diode, a first conductive block, and a first conductive connection structure. The first light emitting diode is disposed on a corresponding first pad structure. The first conductive block is disposed on a corresponding second pad structure. The first conductive connection structure electrically connects the first light emitting diode to the first conductive block. The molding layer is located above the circuit substrate and surrounds the first light emitting diode and the first conductive block. The first conductive connection structure is located on the molding layer.

A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.