An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

The semiconductor device includes an element support, first and second semiconductor elements on the element support, an insulating element insulating the first and the second semiconductor elements from each other, and an insulating substrate. The insulating element includes a first transceiver electrically connected to the first semiconductor element, a second transceiver electrically connected to the second semiconductor element, and an interfacing member for transmitting and receiving signals between the first and the second transceivers. The interfacing member is closer to the element support than the first and the second transceivers. The insulating substrate is between the element support and the insulating element and bonded to the element support. The insulating element is bonded to the insulating substrate.

A semiconductor device includes a low-voltage side frame configured to be connected to a low-voltage chip driven by an input voltage and connected to a ground potential; and a high-voltage side frame configured to be insulated from the low-voltage side frame and connected to a high-voltage chip supplied with a supply voltage having a higher voltage than the input voltage. The high-voltage side frame is connected to a reference potential.

A semiconductor device includes a first die pad, a first semiconductor element, a second die pad, a second semiconductor element, a sealing resin, a first lead, a second lead, a third lead, and a fourth lead. The first lead, the second lead, the third lead, and the fourth lead are each spaced apart from the third side and the fourth side of the sealing resin and are exposed externally from either the first side surface or the second side surface of the sealing resin. Viewed in a third direction perpendicular to the first direction and the second directions, an area of the first die pad is larger than an area of the second die pad. Viewed in the third direction, each of the first lead and the third lead is separated away in the first direction from a first virtual line toward a side where the first side surface of the sealing resin is located.

An encapsulated integrated circuit includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. Within the encapsulation material, a phononic bandgap structure is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons produced by the IC die when the IC die is operating.

In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

Semiconductor device packages including leads for enhanced video bandwidth and related operating criteria are described. An example package includes a flange having a top surface, a frame secured to the flange, and a pair of output leads. The frame forms an air cavity bounded in part by the top surface of the flange. The pair of output leads extend from outside the frame, through at least a portion of the frame, and to within the air cavity. The package also includes a decoupling lead positioned between the pair of output leads. The package also includes a second decoupling lead positioned between the pair of output leads in some examples. The decoupling lead or leads between the output leads facilitate the use of off-package decoupling capacitors to meet video bandwidth and other operating specifications. The package can also include one or more additional decoupling leads between input leads.

A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a nanoparticle layer of a second material on top of and in contact with surface, and a nanoparticle layer of a third material on top of and in contact with the nanoparticle layer of the second material. The nanoparticles of the third material adhere to the nanoparticles of the second material. The substrate region adjoining surface comprises an admixture of the second material in the first material. A fourth material contacts and chemically/mechanically bonds to the nanoparticle layer of the third material.

An example packaged IC includes a lead frame having a supply pin and a ground pin. The supply pin includes first and second supply leads extending from a proximal portion of the supply pin. The ground pin includes first and second ground leads extending from a proximal portion of the ground pin. A first IC network has a first supply terminal coupled to the first supply lead via a first conductor (e.g., bond wire or bump bond). The first IC network also has a first ground terminal coupled to the first ground lead via a second conductor. A second IC network has a second supply terminal coupled to the second supply lead via a third conductor. The second IC network also has a second ground terminal coupled to the second ground lead via a fourth conductor.

A semiconductor die is arranged at a mounting region of a surface of a substrate. A substrate includes electrically conductive leads around a die pad including a mounting region. A metallic layer is located at one or more portions of the substrate including the mounting region. A semiconductor die is arranged at a mounting region. The metallic layer is selectively exposed at portions less than all of the metallic layer to an oxidizing plasma to produce a patterned oxide layer including oxides of metallic material in the metallic layer. An electrically insulating encapsulation is molded onto the surface of the substrate to encapsulate the semiconductor die. The oxides of metallic material in the patterned oxide layer facilitate adhesion of the electrically insulating encapsulation to the surface of the substrate.