A semiconductor arrangement includes first and second controllable semiconductor devices forming a half-bridge arrangement, each controllable semiconductor device including a control electrode and a controllable load path between a first load electrode and a second load electrode. At least one gate driver is configured to generate one or more control signals for one or more of the controllable semiconductor devices. The first controllable semiconductor device is arranged on and electrically coupled to a first lead frame of a plurality of lead frames. The second controllable semiconductor device is arranged on and electrically coupled to a second lead frame of the plurality of lead frames. The controllable semiconductor devices and the at least one gate driver are arranged in a molded package. Each lead frames is partly covered by the molded package and has at least one surface or section that is not covered by the molded package.

A semiconductor device includes a plurality of bonding pads which are constituted by an uppermost layer of a wiring layers, first and third bonding pads connected to an external power supply of the semiconductor chip, second and fourth bonding pads connected to the ground, a fifth bonding pad connected to the third bonding pad via the first inner wiring, and a sixth bonding pad connected to the fourth bonding pad via the second inner wiring, wherein there is no wiring constituting a circuit in one layer just below the uppermost layer at the first and second bonding pads, and there is a wiring constituting the circuit in the one layer just below the uppermost layer at the third to sixth bonding pads.

A semiconductor device includes a cooling base board and an insulated circuit substrate. On a front surface of an insulated board on the insulated circuit substrate, a high potential circuit pattern on which a semiconductor chip is mounted, an intermediate potential circuit pattern on which a semiconductor chip is mounted, a low potential circuit pattern, and a control circuit pattern are disposed so as to straddle a center line of the cooling base board. The intermediate potential circuit pattern includes a second chip mounting region, an output wiring connection region and an interconnect wiring region that form a U-shaped portion in which the high potential circuit pattern having a semiconductor chip thereon is disposed. The control circuit pattern is disposed so as to straddle the center line and faces the opening of the U-shaped portion.

In one example, an electronic device, comprises a substrate comprising a first side and a second side opposite to the first side, wherein the substrate comprises dimples on the first side of the substrate, an electronic component over the first side of the substrate, an encapsulant over the first side of the substrate and covering a lateral side of the electronic component, and a first interconnect in the encapsulant and coupled to the electronic component and the substrate. Other examples and related methods are also disclosed herein.

A semiconductor arrangement includes first and second semiconductor packages separate from one another. Each semiconductor package includes a die carrier having opposite first and second main faces, a transistor die disposed on the first main face, a first lead connected to a first load electrode of the transistor die, a second lead connected to a gate electrode of the transistor die, and an encapsulant embedding at least part of the first main face of the die carrier, inner portions of the leads and the transistor die. The first lead of the first semiconductor package is electrically connected to the first lead of the second semiconductor package, forming a source-source connection. The second lead of the first semiconductor package and the second lead of the second semiconductor package are arranged between the first semiconductor package and the second semiconductor package.

A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

The present disclosure is directed to semiconductor packages manufactured utilizing a leadframe with varying thicknesses. The leadframe with varying thicknesses has a reduced likelihood of deformation while being handled during the manufacturing of the semiconductor packages as well as when being handled during a shipping process. The method of manufacturing is not required to utilize a leadframe tape based on the leadframe with varying thicknesses. This reduces the overall manufacturing costs of the semiconductor packages due to the reduced materials and steps in manufacturing the semiconductor packages as compared to a method that utilizes a leadframe tape to support a leadframe. The semiconductor packages may include leads of varying thicknesses formed by utilizing the leadframe of varying thicknesses to manufacture the semiconductor packages.

A semiconductor device includes: a first terminal and a second terminal; a first conductive member that is electrically connected to the first terminal; a semiconductor chip that is provided on the first conductive member; a second conductive member that is provided on the semiconductor chip and electrically connected to the second terminal; a first insulator that is provided on the second conductive member and covers the semiconductor chip; a conductive plate that is provided on at least a part of the first insulator; and a post that is electrically connected to the conductive plate and extends along a side surface of the first insulator.

A semiconductor device includes an active layer having an active region, a source electrode and a drain electrode disposed on the active region of the active layer and extending along a first direction, a source metal layer disposed on the active region and electrically connected to the source electrode, a drain metal layer disposed on the active region and electrically connected to the drain electrode, and a source pad disposed on the active region. The source metal layer extends along a first direction and has a trapezoid shape in a plan view. The drain metal layer extends along the first direction and has a trapezoid shape in the plan view. The source pad is electrically connected to the source metal layer, and the source pad includes a body portion extending along a second direction and a branch portion extending along the first direction.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.